Silicon Laboratories SI4421 Datasheet

Si4421 PIN ASSIGNMENT This document refers to Si4421-IC rev A1. See www.silabs.com/integration for any applicable errata. See back page for orde

Si4421 AC Characteristics (PLL parameters) Symbol Parameter Conditions/Notes Min Typ Max Units fref PLL reference frequency (Note 2) 9 10 1

Si4421 AC Characteristics (Transmitter) Symbol Parameter Conditions/Notes Min Typ Max Units IOUT Open collector output DC current Programmabl

Si4421 Note 1: Measured with disabled clock output buffer Note 2: Not using a 10 MHz crystal is allowed but not recommended because all crystal ref

Si4421 CONTROL INTERFACE Commands to the transmitter are sent serially. Data bits on pin SDI are shifted into the device upon the rising edge of the c

Si4421 Control Commands Control Command Related Parameters/Functions Related control bits 1 Configuration Setting Command Frequency band, crysta

Si4421 15 Description of the Control Commands 1. Configuration Setting Command Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 POR 1 0 0 0 0 0 0 0 el

Si4421 Logic connections between power control bits: Edge detectoreteresebbexenable crystal oscillator enable baseband circuitsenable RF front endenab

Si4421 3. Frequency Setting Command Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 POR 1 0 1 0 f11 f10 f9 f8 f7 f6 f5 f4 f3 f2 f1 f0 A680h The 12-

Si4421 Bits 9-8 (d1 to d0): VDI (valid data indicator) signal response time setting: d1 d0 Response 0 0 Fast 0 1 Medium 1 0 Slow 1 1 Always on

Si4421 Bits 4-3 (g1 to g0): LNA gain select: g1 g0 Gain relative to maximum [dB] 0 0 0 0 1 -6 1 0 -14 1 1 -20 Bits 2-0 (r2 to r0): RSSI dete

Si4421 2 DETAILED FEATURE-LEVEL DESCRIPTION The Si4421 FSK transceiver is designed to cover the unlicensed frequency bands at 433, 868 and 915 MHz.

Si4421 Bits 2-0 (f2 to f0): DQD threshold parameter. The Data Quality Detector is a digital processing part of the radio, connected to the demodulator

Si4421 Bit 1 (ff): FIFO fill will be enabled after synchron pattern reception. The FIFO fill stops when this bit is cleared. Bit 0 (dr): Disables the

Si4421 Bit 5-4 (rl1 to rl0): Range limit. Limits the value of the frequency offset register to the next values: rl1 rl0 Max deviation 0 0 No rest

Si4421 23 There are four operation modes: 1. (a1=0, a0=0) Automatic operation of the AFC is off. Strobe bit can be controlled by the microcontroller

Si4421 12. PLL Setting Command Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 POR 1 1 0 0 1 1 0 0 0 ob1 ob0 1 dly ddit 1 bw0 CC77h Bits 6-5 (ob1-ob0)

Si4421 14. Wake-Up Timer Command Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 POR 1 1 1 r4 r3 r2 r1 r0 m7 m6 m5 m4 m3 m2 m1 m0 E196h The wa

Si4421 Application Proposal for LPDM (Low Power Duty-Cycle Mode) Receivers: 16. Low Battery Detector and Microcontroller Clock Divider Command Bit 15

Si4421 17. Status Read Command Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 POR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0000h The read command starts with a

Si4421 INTERRUPT HANDLING In order to achieve low power consumption there is an advanced event handling circuit implemented. The device has a very low

Si4421 The best practice in interrupt handling is to start with a status read when interrupt occurs, and then make a decision based on the status byte

Si4421 3 Data Validity Blocks RSSI A digital RSSI output is provided to monitor the input signal level. It goes high if the received signal strength

Si4421 Typical TX register usage et bit(enable transmitter)TX data SPI commands(nSEL, SCK, SDI)enableSynthesizer / PAPASynt.nIRQSDO**et = 1Power Man0x

Si4421 RX FIFO BUFFERED DATA READ In this operating mode, incoming data are clocked into a 16-bit FIFO buffer. The receiver starts to fill up the FIFO

Si4421 CRYSTAL SELECTION GUIDELINES The crystal oscillator of the Si4421 requires a 10 MHz parallel mode crystal. The circuit contains an integrated l

Si4421 RX-TX ALIGNMENT PROCEDURES RX-TX frequency offset can be caused only by the differences in the actual reference frequency. To minimize these er

Si4421 RESET MODES The chip will enter into reset mode if any of the following conditions are met:  Power-on reset: During a power up sequence until

Si4421 Sensitive Reset Enabled, Ripple on Vdd: timeVddReset threshold voltage (600mV)nRes output HL1.6VReset ramp line (100mV/ms) Sensitive reset disa

Si4421 TYPICAL PERFORMANCE CHARACTERISTICS Channel Selectivity and Blocking: 01020304050607080900123456789101112CW interferer offset from carrier [MHz

Si4421 BER Curves in 433 MHz Band: 10-610-510-410-310-210-111.2k2.4k4.8k9.6k19.2k38.4k57.6k115.2k-120 -115 -110 -105 -100 -95 -90 BER Curves in 868

Si4421 Receiver Sensitivity over Ambient Temperature (433 MHz, 2.4 kbps,  fFSK: 45 kHz, BW: 67 kHz): 434 MHz-115-112-109-106-103-100-50-25 0 25507510

Si4421 REFERENCE DESIGNS Evaluation Board with 50 Ohm Matching Network Schematics CLK_OUTARSSIC8C10C9 C11L1L4L2L3ANT********* See values in the table*

Si4421 PACKAGE PIN DEFINITIONS Pin type key: D=digital, A=analog, S=supply, I=input, O=output, IO=input/output Pin Name Type Function 1 SDI DI

Si4421 Notes: 1. SRF, DCR and Q should be similar if components from other manufacturer used 2. The SRF should be twice as much as the operation fre

Si4421 Evaluation Board with Resonant PCB Antenna (BIFA) Schematics *** See values in the tableL11234567891011 1213 1415 1617 1819 2021 2223 2425 26

Si4421 PCB Layout (Antenna designed for 868/915 MHz band) Top View Bottom View 42

Si4421 43 PACKAGE INFORMATION 16-pin TSSOP Detail “A””Gauge Plane0. 25Section B-BSee Detail “A”Min. Nom. Max. Min. Nom. Max.740,002,1A600,0200,051

Si4421 RELATED PRODUCTS AND DOCUMENTS Si4421 Universal ISM Band FSK Transceiver DESCRIPTION ORDERING NUMBER Si4421 16-pin TSSOP Si4421-IC CC16 Rev

Si4421 45

Si4421 5 Internal Pin Connections Pin Name Internal connection 1 SDI 2 SCK 3 nSEL PAD1.5kVSSVDD 4 SDO 5 nIRQ FSK DATA 6 nFFS DLCK CFIL 7 FFIT

Si4421 PIN6 Logic Diagram (FSK / DATA / nFFS) PIN10 Logic Diagram (nRES I/O) * Note: These pins can be left floating. 6

Si4421 7 Typical Application Typical application with FIFO usage C3 C210nX110MHzC12.2uSi442113425768910111213141516VDDSCKSDOnIRQP4P3P1P2SDICLKinnSEL

Si4421 GENERAL DEVICE SPECIFICATIONS All voltages are referenced to Vss, the potential on the ground reference pin VSS. Absolute Maximum Ratings (non-

Si4421 ELECTRICAL SPECIFICATION Test Conditions: Top = 27 oC; Vdd = Voc = 3.3 V DC Characteristics Symbol Parameter Conditions/Notes Min Typ Max