Silicon Laboratories SI5375 User Manual

Rev. 1.0 8/12 Copyright © 2012 by Silicon Laboratories Si5375Si53754-PLL ANY-FREQUENCY PRECISION CLOCK MULTIPLIER/JITTER ATTENUATORFeaturesApplication

Si537510 Rev. 1.0Table 4. Microprocessor Control(VDD= 1.8 ± 5%, 2.5 ±10%, TA= –40 to 85 °C)Parameter Symbol Test Condition Min Typ Max UnitI2C Bus Lin

Si5375Rev. 1.0 11Table 5. Performance SpecificationsVDD= 1.8 V ±5% or 2.5 V ±10%, TA= –40 to 85 °CParameter Symbol Test Condition Min Typ Max UnitPLL

Si537512 Rev. 1.0Table 6. Thermal Characteristics1,2Parameter Symbol Test Condition Min Typ Max UnitMaximum Junction Temperature—125—°CThermal Resista

Si5375Rev. 1.0 132. Typical Application SchematicFigure 3. Typical Application SchematicDSPLLSi5375DSPLLDSPLLDSPLLOTU10GESONETOTUXOXFPXFPXFPXFPXFPXFP

Si537514 Rev. 1.03. Typical Phase Noise Plot622.08 MHz input641.52 MHz output321 fs RMS jitter (12 kHz to 20 MHz)Figure 4. Si5375 Phase Noise P

Si5375Rev. 1.0 154. Functional DescriptionFigure 5. Functional Block DiagramThe Si5375 is a highly integrated jitter-attenuating clock multiplier tha

Si537516 Rev. 1.05. Si5375 Application Examples and Suggestions5.1. Schematic and PCB LayoutFor a typical application schematic and PCB layout, see

Si5375Rev. 1.0 175.5. Reference Oscillator SelectionCare should be taken during the selection of the external oscillator that is connected to the OSC

Si537518 Rev. 1.05.7. OSC_P and OSC_N ConnectionFigures 7, 8, and 9 show examples of connecting various OSC reference sources to the OSC_P and OSC_N

Si5375Rev. 1.0 196. Register MapThe Si5375 has four identical register maps for each DSPLL having a unique I2C address. The I2C address is11010 [A1]

Si53752 Rev. 1.0Functional Block DiagramCKIN1P_B÷ N31DSPLL®BCKIN1N_B÷ N32fOSC÷ NC1_HSInput Monitorf3÷ N2Status / ControlPLL BypassHigh PSRR Voltage Re

Si537520 Rev. 1.025 N1_HS[2:0]31 NC1_LS[19:16]32 NC1_LS[15:8]33 NC1_LS[7:0]40 N2_HS[2:0] N2_LS[19:16]41 N2_LS[15:8]42 N2_LS[7:0]43 N31[18:16]44 N31[15

Si5375Rev. 1.0 217. Register DescriptionsReset value = 0001 0100 Register 0.Bit D7 D6 D5 D4D3D2 D1 D0Name FREE_RUN CKOUT_ALWAYS_ON BYPASS_REGType R R

Si537522 Rev. 1.0 Reset value = 0100 0010 Register 2.BitD7D6D5D4D3D2D1D0Name BWSEL_REG [3:0] RATE_REG [3:0]Type R/W R/WBit Name Function7:4 BWSEL_REG

Si5375Rev. 1.0 23Reset value = 0000 0101Reset value = 1110 1101 Register 3.Bit D7 D6 D5 D4 D3 D2 D1 D0Name VCO_FREEZE SQ_ICALType RRR/W R/WRRRRBit Nam

Si537524 Rev. 1.0Reset value = 0010 1101Reset value = 0000 0000 Register 6.BitD7D6D5D4D3D2D1D0Name SFOUT_REG [2:0]Type RRRRR R/WBit Name Function7:3 R

Si5375Rev. 1.0 25Reset value = 0000 0000Reset value = 0100 0000 Register 10.BitD7D6D5D4D3 D2 D1D0Name DSBL_REGType RRRRR R/W RRBit Name Function7:3 Re

Si537526 Rev. 1.0Reset value = 0000 0000Reset value = 1000 0000 Register 16.BitD7D6D5D4D3D2D1D0Name CLAT [7:0]Type R/WBit Name Function7:0 CLAT [7:0]

Si5375Rev. 1.0 27Reset value = 0000 0000Reset value = 0010 1100 Register 18.BitD7D6D5D4D3D2D1D0Name FLAT [7:0]Type R/WBit Name Function7:0 FLAT [7:0]

Si537528 Rev. 1.0Reset value = 0011 1110Reset value = 1111 1111 Register 20.BitD7D6D5D4D3D2D1D0Name LOL_PIN IRQ_PINType RRRRRWR/WR/WBit Name Function7

Si5375Rev. 1.0 29Reset value = 1101 1111 Register 22.BitD7D6D5D4D3D2 D1 D0Name LOL_POL IRQ_POLType RRRRRRR/WR/WBit Name Function7:3 Reserved1 LOL_POL

Si5375Rev. 1.0 3TABLE OF CONTENTSSection Page1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Si537530 Rev. 1.0Reset value = 0001 1111Reset value = 0011 1111 Register 23.BitD7D6D5D4D3D2 D1 D0Name LOS_ MSK LOSX_ MSKType RRRRRR R/W R/WBit Name Fu

Si5375Rev. 1.0 31Reset value = 0010 0000Reset value = 0000 0000 Register 25.BitD7D6D5D4D3D2D1D0Name N1_HS [2:0]Type R/W RRRRRBit Name Function7:5 N1_H

Si537532 Rev. 1.0Reset value = 0000 0000Reset value = 0011 0001 Register 32.BitD7D6D5D4D3D2D1D0Name NC1_LS [15:8]Type R/WBit Name Function7:0 NC1_LS [

Si5375Rev. 1.0 33Reset value = 1100 0000 Register 40.BitD7D6D5D4D3D2D1D0Name N2_HS [2:0] N2_LS [19:16]Type R/W R R/WBit Name Function7:5 N2_HS [2:0] N

Si537534 Rev. 1.0Reset value = 0000 0000Reset value = 1111 1001 Register 41.BitD7D6D5D4D3D2D1D0Name N2_LS [15:8]Type R/WBit Name Function7:0 N2_LS [15

Si5375Rev. 1.0 35Reset value = 0000 0000Reset value = 0000 0000 Register 43.BitD7D6D5D4D3D2D1D0Name N31 [18:16]Type RRRRR R/WBit Name Function7:3 Rese

Si537536 Rev. 1.0Reset value = 0000 1001Reset value = 0000 0000 Register 45.BitD7D6D5D4D3D2D1D0Name N31[7:0]Type R/WBit Name Function7:0 N31[7:0] N31[

Si5375Rev. 1.0 37Reset value = 0000 0000Reset value = 0000 1001 Register 47.BitD7D6D5D4D3D2D1D0Name N32[15:8]Type R/WBit Name Function7:0 N32[15:8] N3

Si537538 Rev. 1.0Reset value = 0010 0000Reset value = 0000 0110 Register 128.BitD7D6D5D4D3D2 D1 D0Name OSC_ACTV_REG CK_ACTV_REGType RRRRRR R RBit Name

Si5375Rev. 1.0 39Reset value = 0000 0001Reset value = 0001 1111 Register 130.Bit D7 D6D5D4D3D2D1 D0Name CLATPROGRESS LOL_INTType R RRRRRR RBit Name Fu

Si53754 Rev. 1.01. Electrical SpecificationsFigure 1. Differential Voltage CharacteristicsFigure 2. Rise/Fall Time CharacteristicsTable 1. Recommende

Si537540 Rev. 1.0Reset value = 0000 0010Reset value = 0000 0100 Register 132.BitD7D6D5D4D3D2D1 D0Name LOL_FLGType RRRRRRR/WRBit Name Function7:2, 0 Re

Si5375Rev. 1.0 41Reset value = 1011 0010Reset value = 0000 0000 Register 135.BitD7D6D5D4D3D2D1D0Name PARTNUM_RO [3:0] REVID_RO [3:0]Type RRBit Name Fu

Si537542 Rev. 1.0Reset value = 0000 1111Reset value = 1111 1111 Register 138.BitD7D6D5D4D3D2D1 D0Name LOS_EN [1:1]Type RRRRRRR R/WBit Name Function7:1

Si5375Rev. 1.0 437.1. ICALThe device registers must be configured for the device operation. After device configuration, a calibrationprocedure must b

Si537544 Rev. 1.08. Pin Descriptions: Si5375Figure 10. Si5375 Pin Configuration (Bottom View)Bottom ViewABCDEFGH178 65432CKIN1P_DCKIN1N_DLOL_DIRQ_CGN

Si5375Rev. 1.0 45Table 9. Si5375 Pin DescriptionsPin # Pin Name I/O Signal LevelDescriptionD4D6F6F4RSTL_ARSTL_BRSTL_CRSTL_DILVCMOSExternal Reset.Activ

Si537546 Rev. 1.0B2A3B3E4C8A8B8C9H7J7H8H9G1H2J2G2GNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGND SupplyGround for each DSPLLq.Must be connected to

Si5375Rev. 1.0 47G5 SCL I LVCMOSI2C Serial Clock.This pin functions as the serial clock input.This pin has a weak pull-down.G6 SDA I/O LVCMOSI2C Seria

Si537548 Rev. 1.09. Ordering GuideOrdering Part NumberInput/Output ClocksPLLBandwidth RangePackage ROHS6Pb-FreeTemperatureRangeSi5375B-A-GL 4/4 60 Hz

Si5375Rev. 1.0 4910. Package OutlineFigure 11 illustrates the package details for the Si5375. Table 10 lists the values for the dimensions shown in t

Si5375Rev. 1.0 5Table 2. DC Characteristics(VDD= 1.8 ± 5%, 2.5 ±10%, TA= –40 to 85 °C)Parameter Symbol Test Condition Min Typ Max UnitSupply Current1I

Si537550 Rev. 1.011. Recommended PCB LayoutFigure 12. PBGA Card LayoutTable 11. Layout DimensionsSymbol MIN NOM MAXX 0.40 0.45 0.50C1 8.00C2 8.00E1 1

Si5375Rev. 1.0 5112. Top Markings12.1. Si5375 Top Marking (PBGA, Lead-Free)Figure 13. Si5375 Top Marking12.2. Top Marking Explanation (PBGA, Lead-F

Si537552 Rev. 1.012.3. Si5375 Top Marking (PBGA, Lead-Finish)12.4. Top Marking Explanation (PBGA, Lead-Finish)Mark Method: LaserLogo Size: 6.1x2.2m

Si5375Rev. 1.0 53DOCUMENT CHANGE LISTRevision 0.16 to Revision 0.2Improved the Functional Block Diagram.Added specifications for different output

Si537554 Rev. 1.0CONTACT INFORMATIONSilicon Laboratories Inc.400 West Cesar ChavezAustin, TX 78701Tel: 1+(512) 416-8500Fax: 1+(512) 416-9669Toll Free:

Si53756 Rev. 1.0Differential Output VoltageCKOVDLVDS 100  load line-to-line500 700 900 mVPPLow Swing LVDS 100  load line-to-line350 425 500 mVPPComm

Si5375Rev. 1.0 72-Level LVCMOS Input PinsInput Voltage LowVILVDD=1.71V — — 0.5 VVDD=2.25V — — 0.7 VInput Voltage HighVIHVDD=1.89V 1.4 — — VVDD=2.25V 1

Si53758 Rev. 1.0Table 3. AC Characteristics(VDD= 1.8 ± 5%, 2.5 ±10%, TA= –40 to 85 °C)Parameter Symbol Test Condition Min Typ Max UnitSingle-Ended Ref

Si5375Rev. 1.0 9Output Duty Cycle Uncertainty @ 622.08 MHzCKODC100  LoadLine-to-LineMeasured at 50% Point (differential)——±40psLVCMOS Input PinsMinim