Silicon Laboratories Stepper Machine User Manual download pdf (Page 10)

AN155

10 Rev. 1.1

regulator. The total worst-case V

current draw for the

board is about 25 mA. This condition occurs when both

LEDS are on and the serial port is running at 115.2 kbps.

This results in a worst-case power dissipation in the

regulator of about 300 mW with the input voltage at 15 V.

The large tab of the SOT223 is connected to a large

ground plane to improve heatsinking.

4.4. Serial Port

The serial port transceiver is a Sipex SP3223U. This is

a 3.3 V RS232 transceiver. The TX and RX pins of the

transceiver are connected to P0.4 and P0.5 of the

C8051F300. Test points are provided for the TX and RX

connections. The extra transceiver channel is used to

loop RTS back to CTS. This ensures that the terminal

will work when hardware handshaking is enabled.

4.5. PC Board Layout

The two-layer printed circuit board layout is divided into

two routing areas with logic circuits on the left and power

circuits on the right. The logic circuitry uses a ground

plane top and bottom. The minimum clearance from pad

to pad for the C8051F300 MLP11 footprint is about 8

mils. The actual PC board layout uses 10 mil traces and

a 10 mil ground plane clearance. The design rule

checker also uses a 10 mil clearance. Only the pads of

the MLP package have less than 10 mils clearance.

Most PC board fabrication companies can readily

manufacture boards with 8 mil clearances; including

most quick-turn PCB companies. But this does limit the

copper weight to 0.5 oz. raw stock with a finished plated

weight of 1 oz.

Using a finished copper weight of 1 oz., the high current

conductors must be very wide. A copper width of

100 mils (2.5 mm) will give a temperature rise of 10 °C

at 5 A. It is not practical to use conductors this wide with

the small SO8 package, so copper pour regions were

used for the motor current conductors. The part

placement is optimized to provide large copper pour

areas for the ground, 12 V supply, clamp, and motor

outputs. This has the benefit of using all available

copper for current conduction and heatsinking. The

inductance for the clamp circuit is also minimized by

using a large ground plane area on the top and a large

12 V plane on the bottom.

The PC board uses a single point grounding scheme

with separate grounds for the digital and power

sections. The grounds are connected together using a

ground test point footprint. This is a contrived

mechanism to permit the integrated PC board software

to manage the grounds separately and ensure there are

no ground loops. A single design rule error may be

generated for the ground test point.

5. Software Design

5.1. Port Configuration

The C8051F300 family of products has a very useful

feature call the Digital Crossbar. Using the Digital

Crossbar, the end user can select which of the many

peripherals can access the port pins.

In the stepper motor reference design P0.0 through

P0.3 are used to drive the stepper motor. The

corresponding bits are set in the XBR0 register causing

the Crossbar to skip these pins. This means that P0.0

through P0.3 are not available as digital I/O for any of

the internal peripherals. Bits 0 through 3 are also set in

the P0MDOUT register. This configures the pins as

push-pull outputs so that they can drive the power

MOSFETs both high and low.

The stepper motor I/O pins can be controlled by either

setting the bits P0.0 to P0.3 one at a time or by writing a

byte to the P0 register. We would like the pins to change

state simultaneously, so we will write a byte to the P0

P0 register as this affects all of the port pins. Any pins

configured as push-pull outputs will be driven high or

low. Pins that are used as inputs may also be used as

open drain outputs. So if we wish these pins to remain

inputs, we must set the corresponding bits to 1 when

writing to P0.

Port pins P0.4 and P0.5 are allocated to the UART by

setting Bit 0 and Bit 1 in the XBR1 register. This puts the

UART in control of these pins. Writing to P0 will have no

effect on pins P0.4 and P0.5. Unlike other peripherals

that are assigned based on priority, the UART pins are

always assigned to P0.4 and P0.5 when enabled. When

using the UART, the corresponding pin skip bits in XBR0

should not be set. Also Bit 4 of P0MDOUT is set to

configure the TX pin as a push-pull output.

The two remaining pins of P0 are used for a status LED

and a control push-button switch. P0.6 was selected for

the LED. The corresponding Bit 6 is set in XBR0 to skip

P0.6. Bit 6 in P0MDOUT is also set to configure the port

pin as a push-pull output. This is not absolutely

necessary since the LED is only driven when low.

P0.7 is used as the push-button switch input. No special

action is required to configure this pin as an input.

However, one must be careful not to allocate pins to any

other peripherals. Since P0.0 through P0.6 have

already been allocated, P0.7 is next on the allocation

chain. There is no pin skip bit for P0.7. For example,

enabling the SYSCLK output would force the SYSCLK

on P0.7. So for P0.7 to be reserved as an input, bits 4

through 7 of XBR1 must be zero.

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Silicon Laboratories Stepper Machine User Manual Page 10

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