Silicon Laboratories SI5316 User Manual

Rev. 1.0 7/12 Copyright © 2012 by Silicon Laboratories Si5316Si5316PRECISION CLOCK JITTER ATTENUATORFeaturesApplicationsDescriptionThe Si5316 is a low

Si531610 Rev. 1.0Figure 3. Three-Level (3L) Input Pins (No External Resistors)Figure 4. Three-Level Input Pins (Example with External Resistors)Table

Si5316Rev. 1.0 11Table 5. Performance Specifications1, 2, 3, 4, 5(VDD= 1.8 ±5%, 2.5 ±10%, or 3.3 V ±10%, TA= –40 to 85 ºC)Parameter Symbol Test Condit

Si531612 Rev. 1.0Table 7. Absolute Maximum RatingsParameter Symbol Value UnitDC Supply Voltage VDD–0.5 to 3.8 VLVCMOS Input Voltage VDIG–0.3 to (VDD +

Si5316Rev. 1.0 132. Typical Phase Noise PlotThe following is the typical phase noise performance of the Si5316. The clock input source was a Rohde an

Si531614 Rev. 1.03. Typical Applications SchematicFigure 6. Si5316 Typical Application CircuitSi5316CSCK1DIV2C1BC2BCK2DIV2FRQSEL[1:0]2LOLBWSEL[1:0]2S

Si5316Rev. 1.0 154. Functional DescriptionThe Si5316 is a precision jitter attenuator for high-speedcommunication systems, including OC-48/STM-16, OC

Si531616 Rev. 1.05. Pin Descriptions: Si5316Table 8. Si5316 Pin Descriptions Pin # Pin Name I/O Signal Level Description1RSTILVCMOSExternal Reset.Act

Si5316Rev. 1.0 1776XBXAIAnalogExternal Crystal or Reference Clock.External crystal should be connected to these pins to use internal oscillator based

Si531618 Rev. 1.021 CS I LVCMOS Input Clock Select.This pin functions as the input clock selector. This input is internally deglitched to prevent inad

Si5316Rev. 1.0 193330SFOUT0SFOUT1I 3-Level* Signal Format Select.Three level inputs that select the output signal format (common mode voltage and diff

Si53162 Rev. 1.0Functional Block DiagramDSPLL®Frequency SelectXtal or RefclockSignal FormatCKIN1CKOUTSignalDetectLoss of SignalBandwidth SelectLoss of

Si531620 Rev. 1.06. Ordering GuideOrdering Part Number Package ROHS6, Pb-Free Temperature RangeSi5316-C-GM 36-Lead 6 x 6 mm QFN Yes –40 to 85 °CNote:

Si5316Rev. 1.0 217. Package Outline: 36-Lead QFNFigure 7 illustrates the package details for the Si5316. Table 9 lists the values for the dimensions

Si531622 Rev. 1.08. Recommended PCB LayoutFigure 8. PCB Land Pattern DiagramFigure 9. Ground Pad Recommended Layout

Si5316Rev. 1.0 23Table 10. PCB Land Pattern DimensionsDimension MIN MAXe 0.50 BSC.E5.42 REF.D5.42 REF.E2 4.00 4.20D2 4.00 4.20GE 4.53 —GD 4.53 —X — 0.

Si531624 Rev. 1.09. Top Marking9.1. Si5316 Top MarkingFigure 10. Si5316 Top Marking9.2. Top Marking ExplanationMark Method: LaserLine 1 Marking: Si

Si5316Rev. 1.0 25DOCUMENT CHANGE LISTRevision 0.23 to 0.24 Changed LVTTL to LVCMOS in Table 2, “Absolute Maximum Ratings,” on page 5. Added Figure 5

Si531626 Rev. 1.0CONTACT INFORMATIONSilicon Laboratories Inc.400 West Cesar ChavezAustin, TX 78701Tel: 1+(512) 416-8500Fax: 1+(512) 416-9669Toll Free:

Si5316Rev. 1.0 3TABLE OF CONTENTSSection Page1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Si53164 Rev. 1.01. Electrical SpecificationsTable 1. Recommended Operating Conditions(VDD= 1.8 ±5%, 2.5 ±10%, or 3.3 V ±10%, TA= –40 to 85 ºC)Paramet

Si5316Rev. 1.0 5Output Clock (CKOUT)1Common Mode CKOVCMLVPECL 100  load line-to-lineVDD–1.42—VDD–1.25VDifferential Output Swing CKOVDLVPECL 100  loa

Si53166 Rev. 1.02-Level LVCMOS Input PinsInput Voltage Low VILVDD=1.71V — — 0.5 VVDD=2.25V — — 0.7 VVDD=2.97V — — 0.8 VInput Voltage High VIHVDD=1.89V

Si5316Rev. 1.0 7Figure 1. Voltage CharacteristicsLVCMOS Output PinsOutput Voltage Low VOLIO=2mAVDD=1.71V——0.4 VIO=2mAVDD=2.97V——0.4 VOutput Voltage Hi

Si53168 Rev. 1.0Table 3. AC Characteristics(VDD= 1.8 ±5%, 2.5 ±10%, or 3.3 V ±10%, TA= –40 to 85 ºC)Parameter Symbol Test Condition Min Typ Max UnitsC

Si5316Rev. 1.0 9Figure 2. Rise/Fall Time CharacteristicsTime to Clear LOL after LOS Cleared tCLRLOLfin unchanged and XA/XB stable.LOS to  LOL—10 —m