Silicon Laboratories SI5366 User Manual

Preliminary Rev. 0.3 2/08 Copyright © 2008 by Silicon Laboratories Si5366This information applies to a product under development. Its characteristics

Si536610 Preliminary Rev. 0.322 AUTOSEL I 3-Level Manual/Automatic Clock Selection.Three level input that selects the method of input clock selec-tion

Si5366Preliminary Rev. 0.3 1150 DBL_FS I 3-Level FS_OUT Disable.This pin performs the following functions:L = Normal operation. Output path is active

Si536612 Preliminary Rev. 0.356 FOS_CTL I 3-Level Frequency Offset Control.This pin enables or disables use of the CKIN2 FOS reference as an input to

Si5366Preliminary Rev. 0.3 137778CKOUT3+ CKOUT3–OMULTIClock Output 3.Differential output clock with a frequency specified by FRQSEL and FRQTBL sett

Si536614 Preliminary Rev. 0.39293CKOUT2+CKOUT2–OMULTIClock Output 2.Differential output clock with a frequency specified by FRQSEL and FRQTBL. Output

Si5366Preliminary Rev. 0.3 153. Ordering GuideOrdering Part Number Package ROHS6, Pb-Free Temperature RangeSi5366-C-GQ 100-Pin 14 x 14 mm TQFP Yes –4

Si536616 Preliminary Rev. 0.34. Package Outline: 100-Pin TQFPFigure 3 illustrates the package details for the Si5366. Table 4 lists the values for th

Si5366Preliminary Rev. 0.3 175. Recommended PCB LayoutFigure 4. PCB Land Pattern Diagram

Si536618 Preliminary Rev. 0.3Table 5. PCB Land Pattern DimensionsDimension MIN MAXe0.50 BSC.E 15.40 REF.D 15.40 REF.E2 3.90 4.10D2 3.90 4.10GE 13.90 —

Si5366Preliminary Rev. 0.3 19DOCUMENT CHANGE LISTRevision 0.1 to Revision 0.2 Updated Table 1, “Performance Specifications,” on page 2. Changed LVTT

Si53662 Preliminary Rev. 0.3Table 1. Performance Specifications (VDD= 1.8 ±5% or 2.5 V ±10%, TA= –40 to 85 ºC)Parameter Symbol Test Condition Min Typ

Si536620 Preliminary Rev. 0.3CONTACT INFORMATIONSilicon Laboratories Inc.400 West Cesar ChavezAustin, TX 78701Tel: 1+(512) 416-8500Fax: 1+(512) 416-96

Si5366Preliminary Rev. 0.3 3Duty Cycle CKODC 45 — 55 %PLL PerformanceJitter Generation JGENfIN = fOUT = 622.08 MHz,LVPECL output format50 kHz–80 MHz—0

Si53664 Preliminary Rev. 0.3Figure 1. Typical Phase Noise PlotJitter Bandwidth RMS Jitter (fs)OC-48, 12 kHz to 20 MHz 374OC-192, 20 kHz to 80 MHz 388O

Si5366Preliminary Rev. 0.3 5Figure 2. Si5366 Typical Application CircuitSi5366CKIN1+CKIN1–CKSEL[1:0]3ALRMOUTCKnBLOLRATE2RSTCKOUT1+CKOUT1–VDDGNDInput C

Si53666 Preliminary Rev. 0.31. Functional DescriptionThe Si5366 is a jitter-attenuating precision clockmultiplier for high-speed communication system

Si5366Preliminary Rev. 0.3 72. Pin Descriptions: Si5366Table 3. Si5366 Pin Descriptions Pin # Pin Name I/O Signal Level Description1, 2, 23, 24, 25,

Si53668 Preliminary Rev. 0.34 FRQTBL I 3-Level Frequency Table Select.This pin selects SONET/SDH, datacom, or SONET/SDH to datacom frequency translati

Si5366Preliminary Rev. 0.3 912 ALRMOUT O LVCMOS Alarm Output Indicator.This pin is an active high alarm output associated with CKIN4 or the frame sync