Silicon Laboratories SI5374 User Manual

Rev. 1.1 1/14 Copyright © 2014 by Silicon Laboratories Si5374Si53744-PLL ANY-FREQUENCY PRECISION CLOCKMULTIPLIER/JITTER ATTENUATORFeaturesApplications

Si537410 Rev. 1.1Device Skew2Output Clock Skew tSKEWof CKOUTn to  of CKOUT_m, CKOUTn and CKOUT_m at same frequency and signal format PHASEOFFSET =

Si5374Rev. 1.1 11Table 5. Performance SpecificationsVDD= 1.8 V ±5% or 2.5 V ±10%, TA= –40 to 85 °CParameter Symbol Test Condition Min Typ Max UnitPLL

Si537412 Rev. 1.1Table 6. Thermal Characteristics1,2Parameter Symbol Test Condition Min Typ Max UnitMaximum Junction Temperature—125—°CThermal Resista

Si5374Rev. 1.1 132. Typical Application Schematic10G PHY10G PHY10G PHY10G PHY4SyncE Recovered ClocksFPGADSPLLDSPLLDSPLLDSPLLPort Independent Timing (

Si537414 Rev. 1.13. Typical Phase Noise Plot 19.44 MHz input 698.8123 MHz OTU4 output 334 fs RMS jitter (12 kHz to 20 MHz)Figure 3. Typical Phase

Si5374Rev. 1.1 154. Functional DescriptionFigure 4. Functional Block DiagramCKIN3P_BCKOUT3N_B÷ N31DSPLL®B÷ NC1÷ NC2CKIN3N_BCKIN4P_B÷ N32CKIN4N_BInter

Si537416 Rev. 1.1The Si5374 is a highly integrated jitter-attenuating clockmultiplier that integrates four fully independent DSPLLsand provides ultra-

Si5374Rev. 1.1 175. Si5374 Application Examples and Suggestions5.1. Schematic and PCB LayoutFor a typical application schematic and PCB layout, seet

Si537418 Rev. 1.1that have high wander. Experience has shown that inspite of having low jitter, some MEMs oscillators havehigh wander, and these devic

Si5374Rev. 1.1 195.7. OSC_P and OSC_N ConnectionFigures 6, 7, and 8 show examples of connectingvarious OSC reference sources to the OSC_P andOSC_N pi

Si53742 Rev. 1.1Functional Block Diagram CKIN3P_BCKOUT3N_B÷ N31DSPLL®B÷ NC1÷ NC2CKIN3N_BCKIN4P_B÷ N32CKIN4N_BInternal OscPLL BypassCKOUT3P_BCKOUT4N_BC

Si537420 Rev. 1.16. Register MapThe Si5374 has four identical register maps for each DSPLL. Each DSPLL has a unique I2C address enablingindependent c

Si5374Rev. 1.1 2133 NC1_LS[7:0]34 NC2_LS[19:16]35 NC2_LS[15:8]36 NC2_LS[7:0]40 N2_HS[2:0] N2_LS[19:16]41 N2_LS[15:8]42 N2_LS[7:0]43 N31[18:16]44 N31[1

Si537422 Rev. 1.17. Register DescriptionsReset value = 0001 0100 Register 0.Bit D7 D6 D5 D4D3D2 D1 D0Name FREE_RUN CKOUT_ALWAYS_ON BYPASS_REGType RR/

Si5374Rev. 1.1 23Reset value = 1110 0100 Register 1.BitD7D6D5D4D3D2D1D0Name CK_PRIOR2 [1:0] CK_PRIOR1 [1:0]Type RR/WR/WBit Name Function7:4 Reserved3

Si537424 Rev. 1.1Reset value = 0100 0010 Register 2.BitD7D6D5D4D3D2D1D0Name BWSEL_REG [3:0] RATE_REG[3:0]Type R/W R/WBit Name Function7:4 BWSEL_REG [3

Si5374Rev. 1.1 25Reset value = 0000 0101 Register 3.BitD7D6D5D4D3D2D1D0Name CKSEL_REG[1:0] DHOLD SQ_ICALType R/W R/W R/W R R R RBit Name Function7:6 C

Si537426 Rev. 1.1Reset value = 0001 0010Reset value = 1110 1101 Register 4.BitD7D6D5D4D3D2D1D0Name AUTOSEL_REG [1:0] HIST_DEL [4:0]Type R/W R R/WBit N

Si5374Rev. 1.1 27Reset value = 0010 1101 Register 6.BitD7D6D5D4D3D2D1D0Name SFOUT2_REG [2:0] SFOUT1_REG [2:0]Type RR R/W R/WBit Name Function7:6 Reser

Si537428 Rev. 1.1Reset value = 0010 1010 Register 7.BitD7D6D5D4D3D2D1D0Name FOSREFSEL [2:0]Type RRRRR R/WBit Name Function7:3 Reserved2:0 FOSREFSEL [2

Si5374Rev. 1.1 29Reset value = 0000 0000Reset value = 1100 0000 Register 8.BitD7D6D5D4D3D2D1D0Name HLOG_2[1:0] HLOG_1[1:0]Type R/W R/W RRRRBit Name Fu

Si5374Rev. 1.1 3TABLE OF CONTENTSSection Page1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Si537430 Rev. 1.1Reset value = 0000 0000Reset value = 0100 0000 Register 10.BitD7D6D5D4 D3 D2 D1 D0Name DSBL2_REG DSBL1_REGType RRRR R/W R/W R RBit Na

Si5374Rev. 1.1 31Reset value = 0010 1100 Register 19.BitD7D6D5D4D3D2D1D0Name FOS_EN FOS_THR [1:0] VALTIME [1:0] LOCKT [2:0]Type R/W R/W R/W R/WBit Nam

Si537432 Rev. 1.1Reset value = 0011 1110 Register 20.BitD7D6D5D4D3D2D1D0Name Write 0 Write 0 LOL_PIN IRQ_PINType RRRRWWR/WR/WBit Name Function7:4 Rese

Si5374Rev. 1.1 33Reset value = 1111 1111 Register 21.BitD7D6D5D4D3D2 D1 D0Name Write 0 Write 0 CK1_ACTV_PIN CKSEL_ PINType WWRRRR R/W R/WBit Name Func

Si537434 Rev. 1.1Reset value = 1101 1111 Register 22.BitD7D6D5D4 D3 D2 D1 D0Name CK_ACTV_POL LOL_POL INT_POLType RRRR R/W R R/W R/WBit Name Function7:

Si5374Rev. 1.1 35Reset value = 0001 1111 Register 23.BitD7D6D5D4D3 D2 D1 D0Name LOS2_ MSK LOS1_ MSK LOSX_ MSKType RRRRR R/W R/W R/WBit Name Function7:

Si537436 Rev. 1.1Reset value = 0011 1111 Register 24.BitD7D6D5D4D3 D2 D1 D0Name FOS2_MSK FOS1_MSK LOL_MSKType RRRRR R/W R/W R/WBit Name Function7:3 Re

Si5374Rev. 1.1 37Reset value = 0010 0000Reset value = 0000 0000 Register 25.BitD7D6D5D4D3D2D1D0Name N1_HS [2:0]Type R/W RRRRRBit Name Function7:5 N1_H

Si537438 Rev. 1.1Reset value = 0000 0000Reset value = 0011 0001 Register 32.BitD7D6D5D4D3D2D1D0Name NC1_LS [15:8]Type R/WBit Name Function7:0 NC1_LS [

Si5374Rev. 1.1 39Reset value = 0000 0000Reset value = 0000 0000 Register 34.BitD7D6D5D4D3D2D1D0Name NC2_LS [19:16]Type RRRR R/WBit Name Function7:4 Re

Si53744 Rev. 1.11. Electrical SpecificationsFigure 1. Differential Voltage CharacteristicsFigure 2. Rise/Fall Time CharacteristicsTable 1. Recommende

Si537440 Rev. 1.1Reset value = 0011 0001 Register 36.BitD7D6D5D4D3D2D1D0Name NC2_LS [7:0]Type R/WBit Name Function7:0 NC2_LS [7:0] NC2_LS [7:0].Sets v

Si5374Rev. 1.1 41Reset value = 1100 0000 Register 40.BitD7D6D5D4D3D2D1D0Name N2_HS [2:0] N2_LS [19:16]Type R/W R R/WBit Name Function7:5 N2_HS [2:0] N

Si537442 Rev. 1.1Reset value = 0000 0000Reset value = 1111 1001 Register 41.BitD7D6D5D4D3D2D1D0Name N2_LS [15:8]Type R/WBit Name Function7:0 N2_LS [15

Si5374Rev. 1.1 43Reset value = 0000 0000Reset value = 0000 0000 Register 43.BitD7D6D5D4D3D2D1D0Name N31 [18:16]Type RRRRR R/WBit Name Function7:3 Rese

Si537444 Rev. 1.1Reset value = 0000 1001Reset value = 0000 0000 Register 45.BitD7D6D5D4D3D2D1D0Name N31_[7:0]Type R/WBit Name Function7:0 N31_[7:0 N31

Si5374Rev. 1.1 45Reset value = 0000 0000Reset value = 0000 1001 Register 47.BitD7D6D5D4D3D2D1D0Name N32_[15:8]Type R/WBit Name Function7:0 N32_[15:8]

Si537446 Rev. 1.1Reset value = 0000 0000 Register 55.BitD7D6D5D4D3D2D1D0Name CLKIN2RATE[2:0] CLKIN1RATE[2:0]Type RR R/W R/WBit Name Function7:6 Reserv

Si5374Rev. 1.1 47Reset value = 0010 0000Reset value = 0000 0110 Register 128.BitD7D6D5D4D3D2 D1 D0Name CK2_ACTV_REG CK1_ACTV_REGType RRRRRR R RBit Nam

Si537448 Rev. 1.1Reset value = 0000 0001 Register 130.Bit D7 D6 D5 D4 D3 D2 D1 D0Name DIGHOLDVALID FOS2_INT FOS1_INT LOL_INTType R R RRRRRRBit Name Fu

Si5374Rev. 1.1 49Reset value = 0001 1111 Register 131.BitD7D6D5D4D3D2D1D0Name LOS2_FLG LOS1_FLG LOSX_FLGType RRRRRR/WR/WR/WBit Name Function7:3 Reserv

Si5374Rev. 1.1 5Table 2. DC Characteristics(VDD= 1.8 ± 5%, 2.5 ±10%, TA= –40 to 85 °C)Parameter Symbol Test Condition Min Typ Max UnitSupply Current1I

Si537450 Rev. 1.1Reset value = 0000 0010 Register 132.BitD7D6D5D4D3D2D1D0Name FOS2_FLG FOS1_FLG LOL_FLGType RRRRR/WR/WR/WRBit Name Function7:4 Reserve

Si5374Rev. 1.1 51Reset value = 0000 0001Reset value = 1010 0010 Register 134.BitD7D6D5D4D3D2D1D0Name PARTNUM_RO [11:4]Type RBit Name Function7:0 PARTN

Si537452 Rev. 1.1Reset value = 0000 0000Reset value = 0000 0000 Register 136.BitD7D6D5D4D3D2D1D0Name RST_REG ICALType R/WR/WRRRRRRBit Name Function7 R

Si5374Rev. 1.1 53Reset value = 0000 1111 Register 138.BitD7D6D5D4D3D2 D1 D0Name LOS2_EN [1:1] LOS1_EN [1:1]Type RRRRRR R/W R/WBit Name Function7:2 Res

Si537454 Rev. 1.1Reset value = 1111 1111 Register 139.Bit D7 D6 D5 D4 D3 D2 D1 D0Name LOS2_EN [0:0] LOS1_EN [0:0] FOS2_EN FOS1_ENType R R R/W R/W R R

Si5374Rev. 1.1 55Reset value = 0000 0000Reset value = 0000 0000 Register 142.BitD7D6D5D4D3D2D1D0Name INDEPENDENTSKEW1 [7:0]Type R/WBit Name Function7:

Si537456 Rev. 1.17.1. ICALThe device registers must be configured for the device operation. After device configuration, a calibrationprocedure must b

Si5374Rev. 1.1 57Table 10. CKOUT_ALWAYS_ON and SQ_ICAL Truth TableCKOUT_ALWAYS_ON SQ_ICAL Results0 0 CKOUT OFF until after the first ICAL0 1 CKOUT OFF

Si537458 Rev. 1.18. Pin Descriptions: Si5374Figure 9. Si5374 Pin Configuration (Bottom View)Bottom ViewABCDEFGH178 65432CKIN1P_DCKIN1N_DLOL_DIRQ_CGND

Si5374Rev. 1.1 59Table 11. Si5374 Pin DescriptionsPin # Pin Name I/O Signal LevelDescriptionD4D6F6F4RSTL_ARSTL_BRSTL_CRSTL_DILVCMOSExternal Reset.Acti

Si53746 Rev. 1.1Single Ended Output SwingCKOVSELVPECL 100  load line-to-line0.5 — 0.93 VPPDifferential Output VoltageCKOVDCML 100  load line-to-line

Si537460 Rev. 1.1B2A3B3E4C8A8B8C9H7J7H8H9G1H2J2G2GNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGND SupplyGround for each DSPLLq.Must be connected to

Si5374Rev. 1.1 61E2C5E8H5LOL_ALOL_BLOL_CLOL_DOLVCMOSDSPLLq Loss of Lock Indicator.These pins function as the active high PLL loss of lock indicator if

Si537462 Rev. 1.1B1A2A5A4A9B9E9D9J9J8J5J6J1H1E1F1CKOUT1P_ACKOUT1N_ACKOUT2P_ACKOUT2N_ACKOUT1P_BCKOUT1N_BCKOUT2P_BCKOUT2N_BCKOUT1P_CCKOUT1N_CCKOUT2P_CCK

Si5374Rev. 1.1 639. Ordering GuideOrdering Part NumberInput/Output ClocksPLLBandwidth RangePackage RoHS6Pb-FreeTemperatureRangeSi5374B-A-GL18/8 4 to

Si537464 Rev. 1.110. Package OutlineFigure 10 illustrates the package details for the Si5374. Table 12 lists the values for the dimensions shown in t

Si5374Rev. 1.1 6511. Recommended PCB LayoutFigure 11. PBGA Card LayoutTable 13. Layout DimensionsSymbol MIN NOM MAXX 0.40 0.45 0.50C1 8.00C2 8.00E1 1

Si537466 Rev. 1.112. Top Markings12.1. Si5374 Top Marking (PBGA, Lead-Free)12.2. Top Marking Explanation (PBGA, Lead-Free)Mark Method: LaserLogo S

Si5374Rev. 1.1 6712.3. Si5374 Top Marking (PBGA, Lead-Finish)12.4. Top Marking Explanation (PBGA, Lead-Finish)Mark Method: LaserLogo Size: 6.1x2.2m

Si537468 Rev. 1.1DOCUMENT CHANGE LISTRevision 0.1 to Revision 0.2 Added 1.8 V operation. Added 40 MHz reference oscillator Corrected Figure 10 titl

Si5374Rev. 1.1 69CONTACT INFORMATIONSilicon Laboratories Inc.400 West Cesar ChavezAustin, TX 78701Tel: 1+(512) 416-8500Fax: 1+(512) 416-9669Toll Free:

Si5374Rev. 1.1 72-Level LVCMOS Input PinsInput Voltage Low VILVDD=1.71V — — 0.5 VVDD=2.25V — — 0.7 VInput Voltage High VIHVDD=1.89V 1.4 — — VVDD=2.25V

Si53748 Rev. 1.1Table 3. AC Characteristics(VDD= 1.8 ± 5%, 2.5 ±10%, TA= –40 to 85 °C)Parameter Symbol Test Condition Min Typ Max UnitSingle-Ended Ref

Si5374Rev. 1.1 9Output Duty Cycle Uncertainty @ 622.08 MHzCKODC100  LoadLine-to-LineMeasured at 50% Point (differential)——±40psLVCMOS Input PinsMinim