Silicon Laboratories SI5368 User Manual

Rev. 1.0 8/12 Copyright © 2012 by Silicon Laboratories Si5368Si5368ANY-FREQUENCY PRECISION CLOCK MULTIPLIER/JITTER ATTENUATORFeaturesApplicationsDescr

Si536810 Rev. 1.0CKOUTn Output Pins(See ordering section for speed grade vs frequency limits)Output Frequency (Output not config-ured for CMOS or Disa

Si5368Rev. 1.0 11Device SkewOutput Clock Skew tSKEW of CKOUTn to  of CKOUT_m, CKOUTn and CKOUT_m at same frequency and signal format PHASEOFFSET=0CK

Si536812 Rev. 1.0Table 4. Microprocessor Control(VDD= 1.8 ± 5%, 2.5 ±10%, or 3.3 V ±10%, TA= –40 to 85 °C)Parameter Symbol Test Condition Min Typ Max

Si5368Rev. 1.0 13SPI SpecificationsDuty Cycle, SCLK tDCSCLK = 10 MHz 40 — 60 %Cycle Time, SCLK tc100 — — nsRise Time, SCLK tr20–80% — — 25 nsFall Time

Si536814 Rev. 1.0Table 5. Jitter GenerationParameter SymbolTest Condition*Min Typ Max GR-253-SpecificationUnitMeasurement FilterDSPLL BW2Jitter Gen OC

Si5368Rev. 1.0 15Table 7. Absolute Maximum LimitsParameter Symbol Test Condition Min Typ Max UnitDC Supply Voltage VDD–0.5 — 3.8 VLVCMOS Input Voltage

Si536816 Rev. 1.0Figure 1. Differential Voltage CharacteristicsFigure 2. Rise/Fall Time CharacteristicsVISE, VOSEVID,VODDifferential I/OsVICM, VOCMSin

Si5368Rev. 1.0 172. Typical Phase Noise PerformanceFigure 3. Typical Phase Noise PlotTable 8. RMS Jitter by BandJitter Band Jitter, RMSSONET_OC48, 12

Si536818 Rev. 1.03. Typical Application CircuitsFigure 4. Si5368 Typical Application Circuit (I2C Control Mode)Si5368CKIN1+CKIN1–INT_ALMCnBLOLRSTCKOU

Si5368Rev. 1.0 19Figure 5. Si5368 Typical Application Circuit (SPI Control Mode)Si5368CKIN1+CKIN1–INT_ALMCnBLOLRSTCKOUT1+CKOUT1–Input ClockSources*Res

Si53682 Rev. 1.0Functional Block DiagramRate SelectI2C/SPI PortClock SelectXtal or RefclockCKOUT2CKIN1CKOUT1CKIN2ControlSkew ControlCKIN3/FSYNC1CKIN4C

Si536820 Rev. 1.04. Functional DescriptionThe Si5368 is a jitter-attenuating precision clock multiplier for applications requiring sub 1 ps rms jitte

Si5368Rev. 1.0 214.2. Further DocumentationConsult the Silicon Laboratories Any-Frequency Precision Clock Family Reference Manual (FRM) for detailedi

Si536822 Rev. 1.05. Register MapAll register bits that are not defined in this map should always be written with the specified Reset Values. Thewriti

Si5368Rev. 1.0 2323 LOS4_MSK LOS3_MSKLOS2_MSK LOS1_MSK LOSX_MSK24 ALIGN_MSK FOS4_MSK FOS3_MSKFOS2_MSK FOS1_MSK LOL_MSK25 N1_HS [2:0] NC1_LS [19:16]26

Si536824 Rev. 1.054N34_[7:0]55CLKIN2RATE_[2:0] CLKIN1RATE[2:0]56CLKIN4RATE_[2:0] CLKIN3RATE[2:0]128CK4_ACTV_REGCK3_ACTV_REGCK2_ACTV_REGCK1_ACTV_REG129

Si5368Rev. 1.0 256. Register DescriptionsReset value = 0001 0100 Register 0.BitD7D6 D5D4D3 D2D1D0Name FREE_RUNCKOUT_ALWAYS_ONCK_CONFIG_REGBYPASS_REGT

Si536826 Rev. 1.0Reset value = 1110 0100 Register 1.BitD7D6D5D4D3D2D1D0Name CK_PRIOR4 [1:0] CK_PRIOR3 [1:0] CK_PRIOR2 [1:0] CK_PRIOR1 [1:0]Type R/W R/

Si5368Rev. 1.0 27Reset value = 0100 0010 Register 2.BitD7D6D5D4D3D2D1D0Name BWSEL_REG [3:0]Type R/W R R R RBit Name Function7:4 BWSEL_REG [3:0] BWSEL_

Si536828 Rev. 1.0Reset value = 0000 0101 Register 3.BitD7D6D5D4D3D2D1D0Name CKSEL_REG [1:0] DHOLD SQ_ICALType R/W R/W R/W R R R RBit Name Function7:6

Si5368Rev. 1.0 29Reset value = 0001 0010 Register 4.BitD7D6D5D4D3D2D1D0Name AUTOSEL_REG [1:0] HIST_DEL [4:0]Type R/W R R/WBit Name Function7:6 AUTOSEL

Si5368Rev. 1.0 3TABLE OF CONTENTSSection Page1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Si536830 Rev. 1.0Reset value = 1110 1101 Register 5.BitD7D6D5D4D3D2D1D0Name ICMOS [1:0] SFOUT2_REG [2:0] SFOUT1_REG [2:0]Type R/W R/W R/WBit Name Func

Si5368Rev. 1.0 31Reset value = 0010 1100 Register 6.BitD7D6D5D4D3D2D1D0Name SFOUT4_REG [2:0] SFOUT3_REG [2:0]Type RR R/W R/WBit Name Function7:6 Reser

Si536832 Rev. 1.0Reset value = 0010 1010 Register 7.BitD7D6D5D4D3D2D1D0Name SFOUT5_REG [2:0] FOSREFSEL [2:0]Type RR R/W R/WBit Name Function7:6 Reserv

Si5368Rev. 1.0 33Reset value = 0000 0000 Register 8.BitD7D6D5D4D3D2D1D0Name HLOG_4[1:0] HLOG_3[1:0] HLOG_2[1:0] HLOG_1[1:0]Type R/W R/W R/W R/WBit Nam

Si536834 Rev. 1.0Reset value = 1100 0000 Register 9.BitD7D6D5D4D3D2D1D0Name HIST_AVG [4:0] HLOG_5 [1:0]Type R/W R R/WBit Name Function7:3 HIST_AVG [4:

Si5368Rev. 1.0 35Reset value = 0000 0000 Register 10.BitD7D6D5D4D3D2D1D0Name DSBL5_REGDSBL4_REGDSBL3_REGDSBL2_REGDSBL1_REGType RRR/WRR/WR/WRRBit Name

Si536836 Rev. 1.0Reset value = 0100 0000 Register 11.BitD7D6D5D4D3D2D1D0Name ALIGN_THR [2:0]PD_CK4 PD_CK3PD_CK2 PD_CK1Type R/W R/W R/W R R/W R/W R/W R

Si5368Rev. 1.0 37Reset value = 1000 1000 Register 12.BitD7D6D5D4D3D2D1D0Name FPW_VALIDFSYNC_ALIGN_REGFSYNC_ALIGN_MODEFSYNC_SWTCH_REGFSKEW_VALIDFSYNC_S

Si536838 Rev. 1.0Reset value = 0000 0001Reset value = 0000 00002 FSYNC_SKEW [16:0]FSYNC_SKEW [16:0].Phase skew control for FSYNCOUT. The resolution of

Si5368Rev. 1.0 39Reset value = 0000 0000Reset value = 0000 0000 Register 15.BitD7D6D5D4D3D2D1D0Name FSYNC_SKEW [7:0]Type R/WBit Name Function7:0 FSYNC

Si53684 Rev. 1.01. Electrical SpecificationsTable 1. Recommended Operating Conditions1Parameter Symbol Test Condition Min Typ Max UnitAmbient Tempera

Si536840 Rev. 1.0Reset value = 1000 0000Reset value = 0000 0000 Register 17.BitD7 D6D5D4D3D2D1D0Name FLAT_VALID FLAT [14:8]Type R/W R/WBit Name Functi

Si5368Rev. 1.0 41Reset value = 0010 1100 Register 19.BitD7D6D5D4D3D2D1D0Name FOS_EN FOS_THR [1:0] VALTIME [1:0] LOCKT [2:0]Type R/W R/W R/W R/WBit Nam

Si536842 Rev. 1.0Reset value = 0011 1100 Register 20.BitD7D6D5D4D3D2D1D0Name ALRMOUT_PINCK3_BAD_PINCK2_BAD_PINCK1_BAD_PINLOL_PIN INT_PINType R R R/WR/

Si5368Rev. 1.0 43Reset value = 1111 1111 Register 21.BitD7D6D5D4D3D2D1D0Name INCDEC_ PINFSYNC_ALIGN_PINCK4_ACTV_PINCK3_ACTV_PINCK2_ACTV_PINCK1_ACTV_PI

Si536844 Rev. 1.0Reset value = 1101 11111 CK1_ACTV_PIN CK1_ACTV_PIN.The CK1_ACTV_REG status bit can be reflected to the CK1_ACTV output pin using the

Si5368Rev. 1.0 45Reset value = 0001 11113 CK_ACTV_ POL CK_ACTV_POL.Sets the active polarity for the CK1_ACTV, CK2_ACTV, CK3_ACTV, and CK4_ACTVsignals

Si536846 Rev. 1.0Reset value = 0011 11112LOS2_MSKLOS2_MSK.Determines if a LOS on CKIN2 (LOS2_FLG) is used in the generation of an interrupt. Writes to

Si5368Rev. 1.0 47Reset value = 0010 00002 FOS2_MSK FOS2_MSK.Determines if the FOS2_FLG is used in the generation of an interrupt. Writes to this reg-i

Si536848 Rev. 1.0Reset value = 0000 0000Reset value = 0011 0001 Register 26.BitD7D6D5D4D3D2D1D0Name NC1_LS [15:8]Type R/WBit Name Function7:0 NC1_LS [

Si5368Rev. 1.0 49Reset value = 0000 0000 Register 28.BitD7D6D5D4D3D2D1D0Name NC2_LS [19:16]Type RRRR R/WBit Name Function7:4 Reserved3:0 NC1_LS [19:0]

Si5368Rev. 1.0 5CKINn Input Pins2Input Common Mode Voltage (Input Thresh-old Voltage)VICM1.8 V ± 5% 0.9 — 1.4 V2.5 V ± 10% 1 — 1.7 V3.3 V ± 10% 1.1 —

Si536850 Rev. 1.0Reset value = 0000 0000Reset value = 0011 0001 Register 29.BitD7D6D5D4D3D2D1D0Name NC2_LS [15:8]Type R/WBit Name Function7:0 NC2_LS [

Si5368Rev. 1.0 51Reset value = 0000 0000Reset value = 0000 0000 Register 31.BitD7D6D5D4D3D2D1D0Name NC3_LS [19:16]Type RRRR R/WBit Name Function7:4 Re

Si536852 Rev. 1.0Reset value = 0011 0001Reset value = 0000 0000 Register 33.BitD7D6D5D4D3D2D1D0Name NC3_LS [7:0]Type R/WBit Name Function7:0 NC3_LS [7

Si5368Rev. 1.0 53Reset value = 0000 0000Reset value = 0011 0001 Register 35.BitD7D6D5D4D3D2D1D0Name NC4_LS [15:8]Type R/WBit Name Function7:0 NC4_LS [

Si536854 Rev. 1.0Reset value = 0000 0000Reset value = 0000 0000 Register 37.BitD7D6D5D4D3D2D1D0Name NC5_LS [19:16]Type RRRR R/WBit Name Function7:4 Re

Si5368Rev. 1.0 55Reset value = 0011 0001Reset value = 1100 0000 Register 39.BitD7D6D5D4D3D2D1D0Name NC5_LS [7:0]Type R/WBit Name Function7:0 NC5_LS [7

Si536856 Rev. 1.0Reset value = 0000 0000Reset value = 1111 1001 Register 41.BitD7D6D5D4D3D2D1D0Name N2_LS [15:8]Type R/WBit Name Function7:0 N2_LS [15

Si5368Rev. 1.0 57Reset value = 0000 0000Reset value = 0000 0000 Register 43.BitD7D6D5D4D3D2D1D0Name N31 [18:16]Type RRRRR R/WBit Name Function7:3 Rese

Si536858 Rev. 1.0Reset value = 0000 1001Reset value = 0000 0000 Register 45.BitD7D6D5D4D3D2D1D0Name N31 [7:0]Type R/WBit Name Function7:0 N31 [7:0] N3

Si5368Rev. 1.0 59Reset value = 0000 0000Reset value = 0000 1001 Register 47.BitD7D6D5D4D3D2D1D0Name N32_[15:8]Type R/WBit Name Function7:0 N32_[15:8]

Si53686 Rev. 1.0Differential Output Volt-ageCKOVDLVDS 100  load line-to-line500 700 900 mVPPLow Swing LVDS 100  load line-to-line350 425 500 mVPPCom

Si536860 Rev. 1.0Reset value = 0000 0000Reset value = 0000 0000 Register 49.BitD7D6D5D4D3D2D1D0Name N33_[18:0]Type RRRRR R/WBit Name Function18:0 N33_

Si5368Rev. 1.0 61Reset value = 0000 1001Reset value = 0000 0000 Register 51.BitD7D6D5D4D3D2D1D0Name N33_[7:0]Type R/WBit Name Function7:0 N33_[7:0] N3

Si536862 Rev. 1.0Reset value = 0000 0000Reset value = 0000 1001 Register 53.BitD7D6D5D4D3D2D1D0Name N34_[15:8]Type R/WBit Name Function7:0 N34_[15:8]

Si5368Rev. 1.0 63Reset value = 0000 0000 Register 55.BitD7D6D5D4D3D2D1D0Name CLKIN2RATE_[2:0] CLKIN1RATE[2:0]Type RR R/W R/WBit Name Function7:6 Reser

Si536864 Rev. 1.0Reset value = 0000 0000 Register 56.BitD7D6D5D4D3D2D1D0Name CLKIN4RATE_[2:0] CLKIN3RATE[2:0]Type RR R/W R/WBit Name Function7:6 Reser

Si5368Rev. 1.0 65Reset value = 0010 0000 Register 128.BitD7D6D5D4D3D2D1D0Name CK4_ACTV_REGCK3_ACTV_REGCK2_ACTV_REGCK1_ACTV_REGType RRRRRRRRBit Name Fu

Si536866 Rev. 1.0Reset value = 0001 1110 Register 129.BitD7D6D5D4D3D2D1D0NameLOS4_INT LOS3_INTLOS2_INT LOS1_INT LOSX_INTType RRRRRRRRBit Name Function

Si5368Rev. 1.0 67Reset value = 0000 0001 Register 130.BitD7 D6D5D4D3D2 D1 D0Name CLAT-PROGRESSDIGHOLD-VALIDALIGN_INTFOS4_INT FOS3_INT FOS2_INT FOS1_IN

Si536868 Rev. 1.0Reset value = 0001 1111 Register 131.BitD7 D6D5D4D3D2 D1 D0Name LOS4_FLGLOS3_FLGLOS2_FLGLOS1_FLGLOSX_FLGType R R R R/W R/W R/W R/W R/

Si5368Rev. 1.0 69Reset value = 0000 0010 Register 132.BitD7D6D5D4D3D2D1D0Name ALIGN_FLGFOS4_FLG FOS3_FLG FOS2_FLG FOS1_FLG LOL_FLG ALIGN_ERR [8,8]Type

Si5368Rev. 1.0 72-Level LVCMOS Input PinsInput Voltage Low VILVDD=1.71V — — 0.5 VVDD=2.25V — — 0.7 VVDD=2.97V — — 0.8 VInput Voltage High VIHVDD=1.89V

Si536870 Rev. 1.0Reset value = 0000 00002FOS1_FLGFOS1_FLG.CLKIN_1 Frequency Offset Flag.0: Normal operation.1: Held version of FOS1_INT. Generates act

Si5368Rev. 1.0 71Reset value = 0000 0100Reset value = 0100 0010 Register 134.BitD7D6D5D4D3D2D1D0Name PARTNUM_RO [11:4]Type RBit Name Function7:0 PARTN

Si536872 Rev. 1.0Reset value = 0000 0000 Register 136.BitD7D6D5D4D3D2D1D0Name RST_REG ICALType R/WR/WRRRRRRBit Name Function7 RST_REG RST_REG.Internal

Si5368Rev. 1.0 73Reset value = 0000 1111 Register 138.BitD7D6D5D4D3D2D1D0Name LOS4_EN[1:1]LOS3_EN[1:1]LOS2_EN[1:1]LOS1_EN [1:1]Type RRRRR/WR/WR/WR/WBi

Si536874 Rev. 1.0Reset value = 1111 1111 Register 139.BitD7D6D5D4D3D2D1D0Name LOS4_EN [0:0]LOS3_EN [0:0]LOS2_EN [0:0]LOS1_EN [0:0]FOS4_EN FOS3_EN FOS2

Si5368Rev. 1.0 75Reset value = 0000 00003FOS4_ENFOS4_EN.Enables FOS on a Per Channel Basis.0: Disable FOS monitoring.1: Enable FOS monitoring.2FOS3_EN

Si536876 Rev. 1.0Reset value = 0000 0001Reset value = 0000 0000Reset value = 0000 0000 Register 141.BitD7D6D5D4D3D2D1D0Name INDEPENDENTSKEW2 [7:0]Type

Si5368Rev. 1.0 77Reset value = 0000 0000Table 10 lists all of the register locations that should be followed by an ICAL after their contents are chang

Si536878 Rev. 1.0Table 10. Register Locations Requiring ICALAddress Register0 BYPASS_REG0 CKOUT_ALWAYS_ON1 CK_PRIOR41 CK_PRIOR31 CK_PRIOR21 CK_PRIOR12

Si5368Rev. 1.0 797. Pin Descriptions: Si53681234567891011121314151648474645444342414039383736353433313029282726 3264616263575859605051525354555649NCF

Si53688 Rev. 1.03-Level Input Pins4Input Voltage Low VILL— — 0.15 x VDDVInput Voltage Mid VIMM0.45 xVDD—0.55xVDDVInput Voltage High VIHH0.85 xVDD——VIn

Si536880 Rev. 1.0Table 11. Si5368 Pin Descriptions Pin # Pin Name I/O Signal Level Description1, 2, 4, 20, 22, 23, 24, 25, 37, 47, 48, 50, 51, 52, 53,

Si5368Rev. 1.0 8111 C3B O LVCMOS CKIN3 Invalid Indicator.This pin performs the CK3_BAD function if CK3_BAD_PIN =1 and is tristated if CK3_BAD_PIN = 0.

Si536882 Rev. 1.021 FS_ALIGN I LVCMOS FSYNC Alignment Control.If FSYNC_ALIGN_PIN = 1 and CK_CONFIG = 1, a logic high on this pin causes the FS_OUT pha

Si5368Rev. 1.0 8354 DEC I LVCMOS Coarse Latency Decrement.A pulse on this pin decreases the input to output device latency by 1/fOSC (approximately 20

Si536884 Rev. 1.060 SCL I LVCMOS Serial Clock.This pin functions as the serial port clock input for both SPI and I2C modes.This pin has a weak pull-do

Si5368Rev. 1.0 8590 CMODE I LVCMOS Control Mode.Selects I2C or SPI control mode for the device.0=I2C Control Mode.1 = SPI Control Mode.This pin must b

Si536886 Rev. 1.08. Ordering GuideOrdering Part NumberOutput Clock Frequency RangePackage ROHS6, Pb-FreeTemperature RangeSi5368A-C-GQ 2 kHz–945 MHz97

Si5368Rev. 1.0 879. Package Outline: 100-Pin TQFPFigure 6 illustrates the package details for the Si5368. Table 12 lists the values for the dimension

Si536888 Rev. 1.010. Recommended PCB LayoutFigure 7. PCB Land Pattern Diagram

Si5368Rev. 1.0 89Table 13. PCB Land Pattern DimensionsDimension MIN MAXe0.50 BSC.E 15.40 REF.D 15.40 REF.E2 3.90 4.10D2 3.90 4.10GE 13.90 —GD 13.90 —X

Si5368Rev. 1.0 9Table 3. AC Specifications(VDD= 1.8 ± 5%, 2.5 ±10%, or 3.3 V ±10%, TA= –40 to 85 °C)Parameter Symbol Test Condition Min Typ Max UnitSi

Si536890 Rev. 1.011. Top Marking: 100-Pin TQFP11.1. Si5368 Top Marking11.2. Top Marking ExplanationMark Method: LaserLogo Size: 9.2 x 3.1 mmCenter-

Si5368Rev. 1.0 91DOCUMENT CHANGE LISTRevision 0.1 to Revision 0.2 Changed LVTTL to LVCMOS in Table 9, “Absolute Maximum Ratings,” on page 18. Update

Si536892 Rev. 1.0CONTACT INFORMATIONSilicon Laboratories Inc.400 West Cesar ChavezAustin, TX 78701Tel: 1+(512) 416-8500Fax: 1+(512) 416-9669Toll Free: