Silicon Laboratories Stepper Machine Specifications Page 1

8k ISP FLASH MCU FamilyC8051F330/1Preliminary Rev. 1.1 12/03 Copyright © 2003 by Silicon Laboratories C8051F330/1-DS11This information applies to a pr

C8051F330/110 Rev. 1.1Figure 15.8. Typical Master Transmitter Sequence...139Figure 15.9. T

C8051F330/1100 Rev. 1.1Access limit setaccording to theFLASH security lockbyteC8051F330/10x00000x1DFFLock ByteReserved0x1DFE0x1E00FLASH memoryorganize

C8051F330/1Rev. 1.1 101 Figure 11.3. FLKEY: FLASH Lock and Key RegisterBits7-0: FLKEY: FLASH Lock and Key RegisterWrite:This register provides a lock

C8051F330/1102 Rev. 1.1Notes

C8051F330/1Rev. 1.1 10312. EXTERNAL RAMThe C8051F330/1 devices include 512 bytes of RAM mapped into the external data memory space. All of these addre

C8051F330/1104 Rev. 1.1Notes

C8051F330/1Rev. 1.1 10513. OSCILLATORSC8051F330/1 devices include a programmable internal high-frequency oscillator, a programmable internal low-fre-q

C8051F330/1106 Rev. 1.1Electrical specifications for the precision internal oscillator are given in Table 13.1 on page 112. Note that the system clock

C8051F330/1Rev. 1.1 107 Figure 13.2. OSCICL: Internal H-F Oscillator Calibration RegisterBit7: UNUSED. Read = 0. Write = don’t care.Bits 6-0: OSCICL:

C8051F330/1108 Rev. 1.113.2. Programmable Internal Low-Frequency (L-F) OscillatorAll C8051F330/1 devices include a programmable low-frequency internal

C8051F330/1Rev. 1.1 10913.3. External Oscillator Drive CircuitThe external oscillator circuit may drive an external crystal, ceramic resonator, capaci

C8051F330/1Rev. 1.1 11Figure 18.8. TL1: Timer 1 Low Byte ...176Figure

C8051F330/1110 Rev. 1.1Figure 13.5. OSCXCN: External Oscillator Control RegisterBit7: XTLVLD: Crystal Oscillator Valid Flag.(Read only when XOSCMD = 1

C8051F330/1Rev. 1.1 11113.3.1. External Crystal ExampleIf a crystal or ceramic resonator is used as an external oscillator source for the MCU, the cir

C8051F330/1112 Rev. 1.1erals (timers, PCA) when the internal oscillator is selected as the system clock. The system clock may be switched on-the-fly b

C8051F330/1Rev. 1.1 11314. PORT INPUT/OUTPUT Digital and analog resources are available through 17 I/O pins. Port pins are organized as two byte-wide

C8051F330/1114 Rev. 1.1Figure 14.2. Port I/O Cell Block DiagramGND/PORT-OUTENABLEPORT-OUTPUTPUSH-PULLVDDVDD/WEAK-PULLUP(WEAK)PORTPADANALOG INPUTAnalog

C8051F330/1Rev. 1.1 11514.1. Priority Crossbar DecoderThe Priority Crossbar Decoder (Figure 14.3) assigns a priority to each I/O function, starting at

C8051F330/1116 Rev. 1.1Registers XBR0 and XBR1 are used to assign the digital I/O resources to the physical I/O Port pins. Note that when the SMBus is

C8051F330/1Rev. 1.1 11714.2. Port I/O InitializationPort I/O initialization consists of the following steps:Step 1. Select the input mode (analog or

C8051F330/1118 Rev. 1.1 Figure 14.5. XBR0: Port I/O Crossbar Register 0Bits7-6: UNUSED. Read = 00b, Write = don’t care.Bit5: CP0AE: Comparator0 Asynch

C8051F330/1Rev. 1.1 119 Figure 14.6. XBR1: Port I/O Crossbar Register 1Bit7: WEAKPUD: Port I/O Weak Pull-up Disable.0: Weak Pull-ups enabled (except f

C8051F330/112 Rev. 1.1Notes

C8051F330/1120 Rev. 1.114.3. General Purpose Port I/OPort pins that remain unassigned by the Crossbar and are not used by analog peripherals can be us

C8051F330/1Rev. 1.1 121 Figure 14.7. P0: Port0 RegisterBits7-0: P0.[7:0]Write - Output appears on I/O pins per Crossbar Registers.0: Logic Low

C8051F330/1122 Rev. 1.1Figure 14.9. P0MDOUT: Port0 Output Mode RegisterBits7-0: Output Configuration Bits for P0.7-P0.0 (respectively): ignored if cor

C8051F330/1Rev. 1.1 123 Figure 14.11. P1: Port1 RegisterBits7-0: P1.[7:0]Write - Output appears on I/O pins per Crossbar Registers.0: Logic Lo

C8051F330/1124 Rev. 1.1Figure 14.13. P1MDOUT: Port1 Output Mode RegisterBits7-0: Output Configuration Bits for P1.7-P1.0 (respectively): ignored if co

C8051F330/1Rev. 1.1 125 Figure 14.15. P2: Port2 RegisterBits7-1: Unused. Read = 0000000b. Write = don’t care.Bit0: P2.0Write - Outpu

C8051F330/1126 Rev. 1.1 Table 14.1. Port I/O DC Electrical CharacteristicsVDD = 2.7 to 3.6V, -40°C to +85°C unless otherwise specifiedPARAMETERS COND

C8051F330/1Rev. 1.1 12715. SMBUSThe SMBus I/O interface is a two-wire, bi-directional serial bus. The SMBus is compliant with the System Manage-ment B

C8051F330/1128 Rev. 1.115.1. Supporting DocumentsIt is assumed the reader is familiar with or has access to the following supporting documents:1. The

C8051F330/1Rev. 1.1 12915.3. SMBus OperationTwo types of data transfers are possible: data transfers from a master transmitter to an addressed slave r

C8051F330/1Rev. 1.1 131. SYSTEM OVERVIEWC8051F330/1 devices are fully integrated mixed-signal System-on-a-Chip MCUs. Highlighted features are listed b

C8051F330/1130 Rev. 1.115.3.2. Clock Low ExtensionSMBus provides a clock synchronization mechanism, similar to I2C, which allows devices with differen

C8051F330/1Rev. 1.1 13115.4. Using the SMBusThe SMBus can operate in both Master and Slave modes. The interface provides timing and shifting control f

C8051F330/1132 Rev. 1.115.4.1. SMBus Configuration RegisterThe SMBus Configuration register (SMB0CF) is used to enable the SMBus Master and/or Slave m

C8051F330/1Rev. 1.1 133Figure 15.4 shows the typical SCL generation described by Equation 15.2. Notice that THIGH is typically twice as large as TLOW.

C8051F330/1134 Rev. 1.1 Figure 15.5. SMB0CF: SMBus Clock/Configuration RegisterBit7: ENSMB: SMBus Enable.This bit enables/disables the SMBus interface

C8051F330/1Rev. 1.1 13515.4.2. SMB0CN Control RegisterSMB0CN is used to control the interface and to provide status information (see Figure 15.6). The

C8051F330/1136 Rev. 1.1Figure 15.6. SMB0CN: SMBus Control RegisterBit7: MASTER: SMBus Master/Slave Indicator.This read-only bit indicates when the SMB

C8051F330/1Rev. 1.1 137Table 15.3. Sources for Hardware Changes to SMB0CNBit Set by Hardware When: Cleared by Hardware When:MASTER• A START is generat

C8051F330/1138 Rev. 1.115.4.3. Data RegisterThe SMBus Data register SMB0DAT holds a byte of serial data to be transmitted or one that has just been re

C8051F330/1Rev. 1.1 13915.5. SMBus Transfer ModesThe SMBus interface may be configured to operate as master and/or slave. At any particular time, it w

C8051F330/114 Rev. 1.1Table 1.1. Product Selection GuideMIPS (Peak)FLASH MemoryRAMCalibrated Internal 24.5 MHz OscillatorInternal 80 kHz OscillatorSMB

C8051F330/1140 Rev. 1.115.5.2. Master Receiver ModeSerial data is received on SDA while the serial clock is output on SCL. The SMBus interface generat

C8051F330/1Rev. 1.1 14115.5.3. Slave Receiver ModeSerial data is received on SDA and the clock is received on SCL. When slave events are enabled (INH

C8051F330/1142 Rev. 1.115.5.4. Slave Transmitter ModeSerial data is transmitted on SDA and the clock is received on SCL. When slave events are enabled

C8051F330/1Rev. 1.1 14315.6. SMBus Status DecodingThe current SMBus status can be easily decoded using the SMB0CN register. In the table below, STATUS

C8051F330/1144 Rev. 1.1Slave Transmitter0100000A slave byte was transmitted; NACK received.No action required (expecting STOP condition).0 0 X001A sla

C8051F330/1Rev. 1.1 14516. UART0UART0 is an asynchronous, full duplex serial port offering modes 1 and 3 of the standard 8051 UART. Enhanced baud rate

C8051F330/1146 Rev. 1.116.1. Enhanced Baud Rate GenerationThe UART0 baud rate is generated by Timer 1 in 8-bit auto-reload mode. The TX clock is gener

C8051F330/1Rev. 1.1 14716.2. Operational ModesUART0 provides standard asynchronous, full duplex communication. The UART mode (8-bit or 9-bit) is selec

C8051F330/1148 Rev. 1.116.2.2. 9-Bit UART 9-bit UART mode uses a total of eleven bits per data byte: a start bit, 8 data bits (LSB first), a programma

C8051F330/1Rev. 1.1 14916.3. Multiprocessor Communications9-Bit UART mode supports multiprocessor communication between a master processor and one or

C8051F330/1Rev. 1.1 15Port 0LatchUART8kbyteFLASH256 byteSRAMPORSFR Bus8051CoreTimer 0,1, 2, 33-ChnlPCA/WDT10-bit100kspsADCAMUXAIN0-AIN15P0DrvVDDXBARRe

C8051F330/1150 Rev. 1.1Figure 16.7. SCON0: Serial Port 0 Control RegisterBit7: S0MODE: Serial Port 0 Operation Mode.This bit selects the UART0 Operati

C8051F330/1Rev. 1.1 151Figure 16.8. SBUF0: Serial (UART0) Port Data Buffer RegisterBits7-0: SBUF0[7:0]: Serial Data Buffer Bits 7-0 (MSB-LSB)This SFR

C8051F330/1152 Rev. 1.1 Table 16.1. Timer Settings for Standard Baud Rates Using The Internal OscillatorFrequency: 24.5 MHzTarget Baud Rate (bps)Baud

C8051F330/1Rev. 1.1 153 Tabl e 16.3. Timer Settings for Standard Baud Rates Using an External OscillatorFrequency: 22.1184 MHzTarget Baud Rate (bps)B

C8051F330/1154 Rev. 1.1 Tabl e 16.5. Timer Settings for Standard Baud Rates Using an External OscillatorFrequency: 11.0592 MHzTarget Baud Rate (bps)B

C8051F330/1Rev. 1.1 15517. ENHANCED SERIAL PERIPHERAL INTERFACE (SPI0)The Enhanced Serial Peripheral Interface (SPI0) provides access to a flexible, f

C8051F330/1156 Rev. 1.117.1. Signal DescriptionsThe four signals used by SPI0 (MOSI, MISO, SCK, NSS) are described below. 17.1.1. Master Out, Slave In

C8051F330/1Rev. 1.1 15717.2. SPI0 Master Mode OperationA SPI master device initiates all data transfers on a SPI bus. SPI0 is placed in master mode by

C8051F330/1158 Rev. 1.1 MasterDevice 2MasterDevice 1MOSIMISOSCKMISOMOSISCKNSSGPIONSSGPIOFigure 17.2. Multiple-Master Mode Connection DiagramFigure 17.

C8051F330/1Rev. 1.1 15917.3. SPI0 Slave Mode OperationWhen SPI0 is enabled and not configured as a master, it will operate as a SPI slave. As a slave,

C8051F330/116 Rev. 1.1Port 0LatchUART8kbyteFLASH256 byteSRAMPORSFR Bus8051CoreTimer 0,1, 2, 33-ChnlPCA/WDTP0DrvXBARResetXTAL1XTAL2ExternalOscillatorCi

C8051F330/1160 Rev. 1.117.5. Serial Clock TimingFour combinations of serial clock phase and polarity can be selected using the clock control bits in t

C8051F330/1Rev. 1.1 161 MSB Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0MISONSS (4-Wire Mode)MSB Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0MOSISCK(CKPOL=0

C8051F330/1162 Rev. 1.117.6. SPI Special Function RegistersSPI0 is accessed and controlled through four special function registers in the system contr

C8051F330/1Rev. 1.1 163Figure 17.9. SPI0CN: SPI0 Control RegisterBit 7: SPIF: SPI0 Interrupt Flag.This bit is set to logic 1 by hardware at the end of

C8051F330/1164 Rev. 1.1Figure 17.10. SPI0CKR: SPI0 Clock Rate RegisterBits 7-0: SCR7-SCR0: SPI0 Clock Rate.These bits determine the frequency of the S

C8051F330/1Rev. 1.1 165Figure 17.11. SPI0DAT: SPI0 Data RegisterBits 7-0: SPI0DAT: SPI0 Transmit and Receive Data.The SPI0DAT register is used to tran

C8051F330/1166 Rev. 1.1 SCK*TMCKHTMCKLMOSITMISMISO* SCK is shown for CKPOL = 0. SCK is the opposite polarity for CKPOL = 1.TMIHFigure 17.12. SPI Mas

C8051F330/1Rev. 1.1 167 SCK*TSENSSTCKHTCKLMOSITSISTSIHMISOTSDTSOH* SCK is shown for CKPOL = 0. SCK is the opposite polarity for CKPOL = 1.TSEZTSDZFig

C8051F330/1168 Rev. 1.1Tabl e 17.1. SPI Slave Timing ParametersPARAMETER DESCRIPTION MIN MAX UNITSMASTER MODE TIMING† (See Figure 17.12 and Figure 17.

C8051F330/1Rev. 1.1 16918. TIMERS Each MCU includes four counter/timers: two are 16-bit counter/timers compatible with those found in the standard 805

C8051F330/1Rev. 1.1 171.1. CIP-51™ Microcontroller Core1.1.1. Fully 8051 CompatibleThe C8051F330/1 family utilizes Silicon Labs' proprietary CIP-

C8051F330/1170 Rev. 1.1Setting the TR0 bit (TCON.4) enables the timer when either GATE0 (TMOD.3) is logic 0 or the input signal /INT0 is active as def

C8051F330/1Rev. 1.1 17118.1.3. Mode 2: 8-bit Counter/Timer with Auto-ReloadMode 2 configures Timer 0 and Timer 1 to operate as 8-bit counter/timers wi

C8051F330/1172 Rev. 1.118.1.4. Mode 3: Two 8-bit Counter/Timers (Timer 0 Only)In Mode 3, Timer 0 is configured as two separate 8-bit counter/timers he

C8051F330/1Rev. 1.1 173Figure 18.4. TCON: Timer Control RegisterBit7: TF1: Timer 1 Overflow Flag.Set by hardware when Timer 1 overflows. This flag can

C8051F330/1174 Rev. 1.1Figure 18.5. TMOD: Timer Mode RegisterBit7: GATE1: Timer 1 Gate Control.0: Timer 1 enabled when TR1 = 1 irrespective of /INT1 l

C8051F330/1Rev. 1.1 175Figure 18.6. CKCON: Clock Control RegisterBit7: T3MH: Timer 3 High Byte Clock Select.This bit selects the clock supplied to the

C8051F330/1176 Rev. 1.1Figure 18.7. TL0: Timer 0 Low ByteBits 7-0: TL0: Timer 0 Low Byte. The TL0 register is the low byte of the 16-bit Timer 0.R/W R

C8051F330/1Rev. 1.1 17718.2. Timer 2Timer 2 is a 16-bit timer formed by two 8-bit SFRs: TL2 (low byte) and TH2 (high byte). Timer 2 may operate in 16-

C8051F330/1178 Rev. 1.118.2.2. 8-bit Timers with Auto-ReloadWhen T2SPLIT is set, Timer 2 operates as two 8-bit timers (TH2 and TL2). Both 8-bit timers

C8051F330/1Rev. 1.1 179Bit7: TF2H: Timer 2 High Byte Overflow Flag.Set by hardware when the Timer 2 high byte overflows from 0xFF to 0x00. In 16 bit m

C8051F330/118 Rev. 1.11.1.3. Additional FeaturesThe C8051F330/1 SoC family includes several key enhancements to the CIP-51 core and peripherals to imp

C8051F330/1180 Rev. 1.1Bits 7-0: TMR2RLL: Timer 2 Reload Register Low Byte. TMR2RLL holds the low byte of the reload value for Timer 2. R/W R/W R/W R/

C8051F330/1Rev. 1.1 18118.3. Timer 3Timer 3 is a 16-bit timer formed by two 8-bit SFRs: TMR3L (low byte) and TMR3H (high byte). Timer 3 may oper-ate i

C8051F330/1182 Rev. 1.118.3.2. 8-bit Timers with Auto-ReloadWhen T3SPLIT is set, Timer 3 operates as two 8-bit timers (TH3 and TL3). Both 8-bit timers

C8051F330/1Rev. 1.1 183Bit7: TF3H: Timer 3 High Byte Overflow Flag.Set by hardware when the Timer 2 high byte overflows from 0xFF to 0x00. In 16 bit m

C8051F330/1184 Rev. 1.1Bits 7-0: TMR3RLL: Timer 3 Reload Register Low Byte. TMR3RLL holds the low byte of the reload value for Timer 3. R/W R/W R/W R/

C8051F330/1Rev. 1.1 18519. PROGRAMMABLE COUNTER ARRAYThe Programmable Counter Array (PCA0) provides enhanced timer functionality while requiring less

C8051F330/1186 Rev. 1.119.1. PCA Counter/TimerThe 16-bit PCA counter/timer consists of two 8-bit SFRs: PCA0L and PCA0H. PCA0H is the high byte (MSB) o

C8051F330/1Rev. 1.1 18719.2. Capture/Compare ModulesEach module can be configured to operate independently in one of six operation modes: Edge-trigger

C8051F330/1188 Rev. 1.119.2.1. Edge-triggered Capture ModeIn this mode, a valid transition on the CEXn pin causes the PCA to capture the value of the

C8051F330/1Rev. 1.1 18919.2.2. Software Timer (Compare) ModeIn Software Timer mode, the PCA counter/timer value is compared to the module's 16-bi

C8051F330/1Rev. 1.1 191.2. On-Chip MemoryThe CIP-51 has a standard 8051 program and data address configuration. It includes 256 bytes of data RAM, wit

C8051F330/1190 Rev. 1.119.2.3. High Speed Output ModeIn High Speed Output mode, a module’s associated CEXn pin is toggled each time a match occurs bet

C8051F330/1Rev. 1.1 19119.2.4. Frequency Output ModeFrequency Output Mode produces a programmable-frequency square wave on the module’s associated CEX

C8051F330/1192 Rev. 1.119.2.5. 8-Bit Pulse Width Modulator ModeEach module can be used independently to generate a pulse width modulated (PWM) output

C8051F330/1Rev. 1.1 19319.2.6. 16-Bit Pulse Width Modulator ModeA PCA module may also be operated in 16-Bit PWM mode. In this mode, the 16-bit capture

C8051F330/1194 Rev. 1.119.3. Watchdog Timer ModeA programmable watchdog timer (WDT) function is available through the PCA Module 2. The WDT is used to

C8051F330/1Rev. 1.1 195Note that the 8-bit offset held in PCA0CPH2 is compared to the upper byte of the 16-bit PCA counter. This offset value is the n

C8051F330/1196 Rev. 1.119.4. Register Descriptions for PCAFollowing are detailed descriptions of the special function registers related to the operati

C8051F330/1Rev. 1.1 197Figure 19.12. PCA0MD: PCA Mode RegisterBit7: CIDL: PCA Counter/Timer Idle Control. Specifies PCA behavior when CPU is in Idle

C8051F330/1198 Rev. 1.1Bit7: PWM16n: 16-bit Pulse Width Modulation Enable.This bit selects 16-bit mode when Pulse Width Modulation mode is enabled (PW

C8051F330/1Rev. 1.1 199 Bits 7-0: PCA0L: PCA Counter/Timer Low Byte. The PCA0L register holds the low byte (LSB) of the 16-bit PCA Counter/Timer.R/W R

C8051F330/12 Rev. 1.1Notes

C8051F330/120 Rev. 1.11.3. On-Chip Debug CircuitryThe C8051F330/1 devices include on-chip Silicon Labs 2-Wire (C2) debug circuitry that provides non-i

C8051F330/1200 Rev. 1.1 Figure 19.16. PCA0CPLn: PCA Capture Module Low ByteBits7-0: PCA0CPLn: PCA Capture Module Low Byte. The PCA0CPLn register hold

C8051F330/1Rev. 1.1 20120. C2 INTERFACEC8051F330/1 devices include an on-chip Silicon Labs 2-Wire (C2) debug interface to allow FLASH programming, bou

C8051F330/1202 Rev. 1.1 Figure 20.3. REVID: C2 Revision ID RegisterThis read-only register returns the 8-bit revision ID: 0x00 (Revision A).Reset Valu

C8051F330/1Rev. 1.1 20320.2. C2 Pin SharingThe C2 protocol allows the C2 pins to be shared with user functions so that in-system debugging, FLASH prog

C8051F330/1204 Rev. 1.1Contact InformationSilicon Laboratories Inc.4635 Boston Lane Austin, TX 78735 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll

C8051F330/1Rev. 1.1 211.4. Programmable Digital I/O and CrossbarC8051F330/1 devices include 17 I/O pins (two byte-wide Ports and one 1-bit-wide Port).

C8051F330/122 Rev. 1.11.6. Programmable Counter ArrayAn on-chip Programmable Counter/Timer Array (PCA) is included in addition to the four 16-bit gene

C8051F330/1Rev. 1.1 231.7. 10-Bit Analog to Digital ConverterThe C8051F330/1 devices include an on-chip 10-bit SAR ADC with a 16-channel differential

C8051F330/124 Rev. 1.11.8. ComparatorsC8051F330/1 devices include an on-chip voltage comparator that is enabled/disabled and configured via user soft-

C8051F330/1Rev. 1.1 251.9. 10-bit Current Output DACThe C8051F330 device includes a 10-bit current-mode Digital-to-Analog Converter (IDA0). The maximu

C8051F330/126 Rev. 1.12. ABSOLUTE MAXIMUM RATINGSTab le 2.1. Absolute Maximum Ratings*PARAMETER CONDITIONS MIN TYP MAX UNITSAmbient temperature under

C8051F330/1Rev. 1.1 273. GLOBAL DC ELECTRICAL CHARACTERISTICSTab le 3.1. Global DC Electrical Characteristics-40°C TO +85°C, 25 MHZ SYSTEM CLOCK UNLES

C8051F330/128 Rev. 1.14. PINOUT AND PACKAGE DEFINITIONSTable 4.1. Pin Definitions for the C8051F330/1NamePin NumbersType DescriptionVDD 3 Power Supply

C8051F330/1Rev. 1.1 29P0.6/CNVSTR15 D I/O orA InD InPort 0.6. See Section 14 for a complete description.ADC0 External Convert Start or IDA0 Update Sou

C8051F330/1Rev. 1.1 3TABLE OF CONTENTS1. SYSTEM OVERVIEW ...

C8051F330/130 Rev. 1.1 3451289106713121115141819201617GNDP0.0GNDVDD/RST/C2CKP2.0/C2DP1.7P1.6P1.5P1.4P1.3P1.2P1.1P1.0P0.7P0.6P0.5P0.4P0.3P0.2P0.1TOP

C8051F330/1Rev. 1.1 31 181EDA2AA1eA3E2ReLBottom ViewSide View235671015141211201916E22D2813D224 x e4 x eDETAIL 1DETAIL 1AABBCCDDb4917Figure 4.2. MLP-

C8051F330/132 Rev. 1.1 Top VieweEDbL0.50 mm0.30 mm0.10 mm0.20 mm0.85 mm0.50 mm0.30 mm0.10 mm0.20 mm0.85 mmE2D20.35 mm0.35 mm0.60 mm0.30 mm0.20 mm0.7

C8051F330/1Rev. 1.1 33 Top ViewEDbL0.50 mm0.30 mm0.10 mm0.20 mm0.85 mm0.50 mm0.30 mm0.10 mm0.20 mm0.85 mm0.35 mm0.35 mmE2D2eOptionalGNDConnection0.2

C8051F330/134 Rev. 1.1Notes

C8051F330/1Rev. 1.1 355. 10-BIT ADC (ADC0, C8051F330 ONLY)The ADC0 subsystem for the C8051F330 consists of two analog multiplexers (referred to collec

C8051F330/136 Rev. 1.15.1. Analog MultiplexerAMUX0 selects the positive and negative inputs to the ADC. Any of the following may be selected as the po

C8051F330/1Rev. 1.1 375.2. Temperature SensorThe typical temperature sensor transfer function is shown in Figure 5.2. The output voltage (VTEMP) is th

C8051F330/138 Rev. 1.15.3. Modes of OperationADC0 has a maximum conversion speed of 200 ksps. The ADC0 conversion clock is a divided version of the sy

C8051F330/1Rev. 1.1 395.3.2. Tracking ModesThe AD0TM bit in register ADC0CN controls the ADC0 track-and-hold mode. In its default state, the ADC0 inpu

C8051F330/14 Rev. 1.19.2.5. Stack ...7

C8051F330/140 Rev. 1.15.3.3. Settling Time RequirementsWhen the ADC0 input configuration is changed (i.e., a different AMUX0 selection is made), a min

C8051F330/1Rev. 1.1 41 Figure 5.5. AMX0P: AMUX0 Positive Channel Select RegisterBits7-5: UNUSED. Read = 000b; Write = don’t care.Bits4-0: AMX0P4-0: AM

C8051F330/142 Rev. 1.1Figure 5.6. AMX0N: AMUX0 Negative Channel Select RegisterBits7-5: UNUSED. Read = 000b; Write = don’t care.Bits4-0: AMX0N4-0: AMU

C8051F330/1Rev. 1.1 43 Figure 5.7. ADC0CF: ADC0 Configuration RegisterBits7-3: AD0SC4-0: ADC0 SAR Conversion Clock Period Bits.SAR Conversion clock i

C8051F330/144 Rev. 1.1Figure 5.9. ADC0L: ADC0 Data Word LSB RegisterBits7-0: ADC0 Data Word Low-Order Bits.For AD0LJST = 0: Bits 7-0 are the lower 8 b

C8051F330/1Rev. 1.1 45 Figure 5.10. ADC0CN: ADC0 Control RegisterBit7: AD0EN: ADC0 Enable Bit.0: ADC0 Disabled. ADC0 is in low-power shutdown.1: ADC0

C8051F330/146 Rev. 1.15.4. Programmable Window DetectorThe ADC Programmable Window Detector continuously compares the ADC0 output registers to user-pr

C8051F330/1Rev. 1.1 47 Figure 5.13. ADC0LTH: ADC0 Less-Than Data High Byte RegisterBits7-0: High byte of ADC0 Less-Than Data WordR/W R/W R/W R/W R/W R

C8051F330/148 Rev. 1.15.4.1. Window Detector In Single-Ended ModeFigure 5.15 shows two example window comparisons for right-justified, single-ended da

C8051F330/1Rev. 1.1 495.4.2. Window Detector In Differential ModeFigure 5.17 shows two example window comparisons for right-justified, differential da

C8051F330/1Rev. 1.1 515.2.SMBus Configuration...12815

C8051F330/150 Rev. 1.1Table 5.1. ADC0 Electrical CharacteristicsVDD = 3.0 V, VREF = 2.40 V (REFSL=0), -40°C TO +85°C UNLESS OTHERWISE SPECIFIEDPARAMET

C8051F330/1Rev. 1.1 516. 10-BIT CURRENT MODE DAC (IDA0, C8051F330 ONLY)The C8051F330 device includes a 10-bit current-mode Digital-to-Analog Converter

C8051F330/152 Rev. 1.16.1.2. Update Output Based on Timer OverflowSimilar to the ADC operation, in which an ADC conversion can be initiated by a timer

C8051F330/1Rev. 1.1 53 Figure 6.3. IDA0CN: IDA0 Control RegisterBit 7: IDA0EN: IDA0 Enable.0: IDA0 Disabled.1: IDA0 Enabled.Bits 6-4: IDA0CM[2:0]

C8051F330/154 Rev. 1.1Figure 6.5. IDA0L: IDA0 Data Word LSB RegisterBits 7-6: IDA0 Data Word Low-Order Bits.Lower 2 bits of the 10-bit Data Word. Bits

C8051F330/1Rev. 1.1 55.Table 6.1. IDAC Electrical Characteristics-40 to +85°C, VDD = 3.0 V Full-scale output current set to 2 mA unless otherwise spec

C8051F330/156 Rev. 1.1Notes

C8051F330/1Rev. 1.1 577. VOLTAGE REFERENCE (C8051F330 ONLY)The Voltage reference MUX on C8051F330/1 devices is configurable to use an externally conne

C8051F330/158 Rev. 1.1 Table 7.1. Voltage Reference Electrical CharacteristicsVDD = 3.0 V; -40°C TO +85°C UNLESS OTHERWISE SPECIFIEDPARAMETER CONDITIO

C8051F330/1Rev. 1.1 598. COMPARATOR0 C8051F330/1 devices include an on-chip programmable voltage comparator, Comparator0, shown in Figure 8.1.The Com

C8051F330/16 Rev. 1.119. PROGRAMMABLE COUNTER ARRAY ...18519.1.PCA Counter/Timer..

C8051F330/160 Rev. 1.1The Comparator output can be polled in software, used as an interrupt source, and/or routed to a Port pin. When routed to a Port

C8051F330/1Rev. 1.1 61Comparator falling-edge occurrence, and the CP0RIF flag is set to logic 1 upon the Comparator rising-edge occur-rence. Once set,

C8051F330/162 Rev. 1.1 Figure 8.3. CPT0CN: Comparator0 Control RegisterBit7: CP0EN: Comparator0 Enable Bit.0: Comparator0 Disabled.1: Comparato

C8051F330/1Rev. 1.1 63Figure 8.4. CPT0MX: Comparator0 MUX Selection RegisterBits7-4: CMX0N2-CMX0N0: Comparator0 Negative Input MUX Select.These bits s

C8051F330/164 Rev. 1.1Figure 8.5. CPT0MD: Comparator0 Mode Selection RegisterBits7-6: UNUSED. Read = 00b, Write = don’t care.Bit5: CP0RIE: Comparator0

C8051F330/1Rev. 1.1 65 Table 8.1. Comparator Electrical CharacteristicsVDD = 3.0 V, -40°C TO +85°C UNLESS OTHERWISE NOTED. PARAMETER CONDITIONS MIN

C8051F330/166 Rev. 1.1Notes

C8051F330/1Rev. 1.1 679. CIP-51 MICROCONTROLLER The MCU system controller core is the CIP-51 microcontroller. The CIP-51 is fully compatible with the

C8051F330/168 Rev. 1.1PerformanceThe CIP-51 employs a pipelined architecture that greatly increases its instruction throughput over the standard 8051

C8051F330/1Rev. 1.1 699.1. INSTRUCTION SETThe instruction set of the CIP-51 System Controller is fully compatible with the standard MCS-51™ instructio

C8051F330/1Rev. 1.1 7LIST OF FIGURES AND TABLES1. SYSTEM OVERVIEWTable 1.1. Product Selection Guide...

C8051F330/170 Rev. 1.1MUL AB Multiply A and B 1 4DIV AB Divide A by B 1 8DA A Decimal adjust A 1 1LOGICAL OPERATIONSANL A, Rn AND Register to A 1 1ANL

C8051F330/1Rev. 1.1 71MOV DPTR, #data16 Load DPTR with 16-bit constant 3 3MOVC A, @A+DPTR Move code byte relative DPTR to A 1 3MOVC A, @A+PC Move code

C8051F330/172 Rev. 1.1CJNE @Ri, #data, rel Compare immediate to indirect and jump if not equal 3 4/5DJNZ Rn, rel Decrement Register and jump if not ze

C8051F330/1Rev. 1.1 739.2. MEMORY ORGANIZATIONThe memory organization of the CIP-51 System Controller is similar to that of a standard 8051. There are

C8051F330/174 Rev. 1.19.2.2. Data MemoryThe CIP-51 includes 256 bytes of internal RAM mapped into the data memory space from 0x00 through 0xFF. The lo

C8051F330/1Rev. 1.1 759.2.6. Special Function RegistersThe direct-access data memory locations from 0x80 to 0xFF constitute the special function regis

C8051F330/176 Rev. 1.1ADC0LTL 0xC5 ADC0 Less-Than Compare Word Low 47AMX0N 0xBA AMUX0 Negative Channel Select 42AMX0P 0xBB AMUX0 Positive Channel Sele

C8051F330/1Rev. 1.1 77PCA0CPM2 0xDC PCA Module 2 Mode Register 198PCA0H 0xFA PCA Counter High 199PCA0L 0xF9 PCA Counter Low 199PCA0MD 0xD9 PCA Mode 1

C8051F330/178 Rev. 1.19.2.7. Register DescriptionsFollowing are descriptions of SFRs related to the operation of the CIP-51 System Controller. Reserve

C8051F330/1Rev. 1.1 79 Figure 9.5. SP: Stack PointerBits7-0: SP: Stack Pointer.The Stack Pointer holds the location of the top of the stack. The stack

C8051F330/18 Rev. 1.1Figure 5.18. ADC Window Compare Example: Left-Justified Differential Data ...49Table 5.1. ADC0 Electrical Charac

C8051F330/180 Rev. 1.1 Figure 9.7. ACC: AccumulatorBits7-0: ACC: Accumulator.This register is the accumulator for arithmetic operations.R/W R/W R/W R/

C8051F330/1Rev. 1.1 819.3. Interrupt HandlerThe CIP-51 includes an extended interrupt system supporting a total of 13 interrupt sources with two prior

C8051F330/182 Rev. 1.19.3.2. External InterruptsThe /INT0 and /INT1 external interrupt sources are configurable as active high or low, edge or level s

C8051F330/1Rev. 1.1 83Table 9.4. Interrupt SummaryInterrupt SourceInterrupt VectorPriority OrderPending FlagBit addressable?Cleared by HW?Enable FlagP

C8051F330/184 Rev. 1.19.3.5. Interrupt Register DescriptionsThe SFRs used to enable the interrupt sources and set their priority level are described b

C8051F330/1Rev. 1.1 85Figure 9.10. IP: Interrupt PriorityBit7: UNUSED. Read = 1, Write = don't care.Bit6: PSPI0: Serial Peripheral Interface (SPI

C8051F330/186 Rev. 1.1Figure 9.11. EIE1: Extended Interrupt Enable 1Bit7: ET3: Enable Timer 3 Interrupt.This bit sets the masking of the Timer 3 inter

C8051F330/1Rev. 1.1 87Figure 9.12. EIP1: Extended Interrupt Priority 1Bit7: PT3: Timer 3 Interrupt Priority Control. This bit sets the priority of the

C8051F330/188 Rev. 1.1Bit7: IN1PL: /INT1 Polarity0: /INT1 input is active low.1: /INT1 input is active high.Bits6-4: IN1SL2-0: /INT1 Port Pin Selectio

C8051F330/1Rev. 1.1 899.4. Power Management ModesThe CIP-51 core has two software programmable power management modes: Idle and Stop. Idle mode halts

C8051F330/1Rev. 1.1 911. FLASH MEMORYTable 11.1. FLASH Electrical Characteristics ...

C8051F330/190 Rev. 1.1Bits7-2: GF5-GF0: General Purpose Flags 5-0. These are general purpose flags for use under software control.Bit1: STOP: Stop Mod

C8051F330/1Rev. 1.1 9110. RESET SOURCESReset circuitry allows the controller to be easily placed in a predefined default condition. On entry to this r

C8051F330/192 Rev. 1.110.1. Power-On ResetDuring power-up, the device is held in a reset state and the /RST pin is driven low until VDD settles above

C8051F330/1Rev. 1.1 9310.2. Power-Fail Reset / VDD MonitorWhen a power-down transition or power irregularity causes VDD to drop below VRST, the power

C8051F330/194 Rev. 1.110.3. External ResetThe external /RST pin provides a means for external circuitry to force the device into a reset state. Assert

C8051F330/1Rev. 1.1 95Figure 10.4. RSTSRC: Reset Source RegisterBit7: UNUSED. Read = 0. Write = don’t care.Bit6: FERROR: FLASH Error Indicator.0: Sour

C8051F330/196 Rev. 1.1Table 10.1. Reset Electrical Characteristics-40°C to +85°C unless otherwise specified.PARAMETER CONDITIONS MIN TYP MAX UNITS/RST

C8051F330/1Rev. 1.1 9711. FLASH MEMORYOn-chip, re-programmable FLASH memory is included for program code and non-volatile data storage. The FLASH memo

C8051F330/198 Rev. 1.111.1.3. FLASH Write ProcedureFLASH bytes are programmed by software with the following sequence:Step 1. Disable interrupts (rec

C8051F330/1Rev. 1.1 9911.2. Non-volatile Data StorageThe FLASH memory can be used for non-volatile data storage as well as program code. This allows d