Silicon Laboratories Stepper Machine Specifications download pdf (Page 82)

C8051F330/1

82 Rev. 1.1

9.3.2. External Interrupts

The /INT0 and /INT1 external interrupt sources are configurable as active high or low, edge or level sensitive. The

IN0PL (/INT0 Polarity) and IN1PL (/INT1 Polarity) bits in the IT01CF register select active high or active low; the

IT0 and IT1 bits in TCON (

Section “18.1. Timer 0 and Timer 1” on page 169) select level or edge sensitive. The

table below lists the possible configurations.

/INT0 and /INT1 are assigned to Port pins as defined in the IT01CF register (see Figure 9.13). Note that /INT0 and

/INT0 Port pin assignments are independent of any Crossbar assignments. /INT0 and /INT1 will monitor their

assigned Port pins without disturbing the peripheral that was assigned the Port pin via the Crossbar. To assign a Port

pin only to /INT0 and/or /INT1, configure the Crossbar to skip the selected pin(s). This is accomplished by setting the

associated bit in register XBR0 (see

Section “14.1. Priority Crossbar Decoder” on page 115 for complete details

on configuring the Crossbar).

IE0 (TCON.1) and IE1 (TCON.3) serve as the interrupt-pending flags for the /INT0 and /INT1 external interrupts,

respectively. If an /INT0 or /INT1 external interrupt is configured as edge-sensitive, the corresponding interrupt-

pending flag is automatically cleared by the hardware when the CPU vectors to the ISR. When configured as level

sensitive, the interrupt-pending flag remains logic 1 while the input is active as defined by the corresponding polarity

bit (IN0PL or IN1PL); the flag remains logic 0 while the input is inactive. The external interrupt source must hold the

input active until the interrupt request is recognized. It must then deactivate the interrupt request before execution of

the ISR completes or another interrupt request will be generated.

9.3.3. Interrupt Priorities

Each interrupt source can be individually programmed to one of two priority levels: low or high. A low priority inter-

rupt service routine can be preempted by a high priority interrupt. A high priority interrupt cannot be preempted. Each

interrupt has an associated interrupt priority bit in an SFR (IP or EIP1) used to configure its priority level. Low prior

ity is the default. If two interrupts are recognized simultaneously, the interrupt with the higher priority is serviced

first. If both interrupts have the same priority level, a fixed priority order is used to arbitrate, given in

Table 9.4.

9.3.4. Interrupt Latency

Interrupt response time depends on the state of the CPU when the interrupt occurs. Pending interrupts are sampled

and priority decoded each system clock cycle. Therefore, the fastest possible response time is 5 system clock cycles:

clock cycle to detect the interrupt and 4 clock cycles to complete the LCALL to the ISR. If an interrupt is pending

when a RETI is executed, a single instruction is executed before an LCALL is made to service the pending interrupt.

Therefore, the maximum response time for an interrupt (when no other interrupt is currently being serviced or the

new interrupt is of greater priority) occurs when the CPU is performing an RETI instruction followed by a DIV as the

next instruction. In this case, the response time is 18

system clock cycles: 1 clock cycle to detect the interrupt, 5 clock

cycles to execute the RETI, 8

clock cycles to complete the DIV instruction and 4 clock cycles to execute the LCALL

to the ISR. If the CPU is executing an ISR for an interrupt with equal or higher priority, the new interrupt will not be

serviced until the current ISR completes, including the RETI and following instruction.

IT0 IN0PL /INT0 Interrupt IT1 IN1PL /INT1 Interrupt

Active low, edge sensitive 10Active low, edge sensitive

11Active high, edge sensitive 11Active high, edge sensitive

00Active low, level sensitive 00Active low, level sensitive

01Active high, level sensitive 01Active high, level sensitive

1 2 ... 77 78 79 80 81 82 83 84 85 86 87 ... 203 204

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