Silicon Laboratories Stepper Machine Specifications download pdf (Page 17)

C8051F330/1

Rev. 1.1 17

1.1. CIP-51™ Microcontroller Core

1.1.1. Fully 8051 Compatible

The C8051F330/1 family utilizes Silicon Labs' proprietary CIP-51 microcontroller core. The CIP-51 is fully compat-

ible with the MCS-51™ instruction set; standard 803x/805x assemblers and compilers can be used to develop soft-

ware. The CIP-51 core offers all the peripherals included with a standard 8052, including four 16-bit counter/timers,

a full-duplex UART with extended baud rate configuration, an enhanced SPI port, 768

bytes of internal RAM,

128

byte Special Function Register (SFR) address space, and 17 I/O pins.

1.1.2. Improved Throughput

The CIP-51 employs a pipelined architecture that greatly increases its instruction throughput over the standard 8051

architecture. In a standard 8051, all instructions except for MUL and DIV take 12 or 24 system clock cycles to exe

cute with a maximum system clock of 12-to-24 MHz. By contrast, the CIP-51 core executes 70% of its instructions in

one or two system clock cycles, with only four instructions taking more than four system clock cycles.

The CIP-51 has a total of 109 instructions. The table below shows the total number of instructions that require each

execution time.

With the CIP-51's maximum system clock at 25 MHz, it has a peak throughput of 25 MIPS. Figure 1.3 shows a com-

parison of peak throughputs for various 8-bit microcontroller cores with their maximum system clocks.

Clocks to Execute 1 2 2/3 3 3/4 4 4/5 5 8

Number of Instructions 26 50 5 14 7 3 1 2 1

ADuC812

8051

(16MHz clk)

Philips

80C51

(33MHz clk)

Microchip

PIC17C75x

(33MHz clk)

Silicon Labs

CIP-51

(25MHz clk)

MIPS

Figure 1.3. Comparison of Peak MCU Execution Speeds

1 2 ... 12 13 14 15 16 17 18 19 20 21 22 ... 203 204

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Silicon Laboratories Stepper Machine Specifications Page 17