Silicon Laboratories Stepper Machine Specifications download pdf (Page 141)

C8051F330/1

Rev. 1.1 141

15.5.3. Slave Receiver Mode

Serial data is received on SDA and the clock is received on SCL. When slave events are enabled (INH = 0), the inter-

face enters Slave Receiver Mode when a START followed by a slave address and direction bit (WRITE in this case)

is received. Upon entering Slave Receiver Mode, an interrupt is generated and the ACKRQ bit is set. Software

responds to the received slave address with an ACK, or ignores the received slave address with a NACK. If the

received slave address is ignored, slave interrupts will be inhibited until the next START is detected. If the received

slave address is acknowledged, zero or more data bytes are received. Software must write the ACK bit after each

received byte to ACK or NACK the received byte. The interface exits Slave Receiver Mode after receiving a STOP.

Note that the interface will switch to Slave Transmitter Mode if SMB0DAT is written while an active Slave Receiver.

Figure 15.10 shows a typical Slave Receiver sequence. Two received data bytes are shown, though any number of

bytes may be received. Notice that the ‘data byte transferred’ interrupts occur before the ACK cycle in this mode.

PWSLAS Data ByteData Byte A AA

S = START

P = STOP

A = ACK

W = WRITE

SLA = Slave Address

Received by SMBus

Interface

Transmitted by

SMBus Interface

Interrupt Interrupt Interrupt

Interrupt

Figure 15.10. Typical Slave Receiver Sequence

1 2 ... 136 137 138 139 140 141 142 143 144 145 146 ... 203 204

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Silicon Laboratories Stepper Machine Specifications Page 141