Silicon Laboratories Stepper Machine Specifications download pdf (Page 78)

C8051F330/1

78 Rev. 1.1

9.2.7. Register Descriptions

Following are descriptions of SFRs related to the operation of the CIP-51 System Controller. Reserved bits should not

be set to logic

l. Future product versions may use these bits to implement new features in which case the reset value

of the bit will be logic

0, selecting the feature's default state. Detailed descriptions of the remaining SFRs are included

in the sections of the datasheet associated with their corresponding system function.

Figure 9.3. DPL: Data Pointer Low Byte

Bits7-0: DPL: Data Pointer Low.

The DPL register is the low byte of the 16-bit DPTR. DPTR is used to access indirectly addressed

FLASH memory or XRAM.

R/W R/W R/W R/W R/W R/W R/W R/W Reset Value

00000000

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:

0x82

Figure 9.4. DPH: Data Pointer High Byte

Bits7-0: DPH: Data Pointer High.

The DPH register is the high byte of the 16-bit DPTR. DPTR is used to access indirectly addressed

FLASH memory or XRAM.

R/W R/W R/W R/W R/W R/W R/W R/W Reset Value

00000000

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:

0x83

1 2 ... 73 74 75 76 77 78 79 80 81 82 83 ... 203 204

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Silicon Laboratories Stepper Machine Specifications Page 78