Silicon Laboratories Stepper Machine Specifications download pdf (Page 138)

C8051F330/1

138 Rev. 1.1

15.4.3. Data Register

The SMBus Data register SMB0DAT holds a byte of serial data to be transmitted or one that has just been received.

Software may safely read or write to the data register when the SI flag is set. Software should not attempt to access

the SMB0DAT register when the SMBus is enabled and the SI flag is cleared to logic

0, as the interface may be in the

process of shifting a byte of data into or out of the register.

Data in SMB0DAT is always shifted out MSB first. After a byte has been received, the first bit of received data is

located at the MSB of SMB0DAT. While data is being shifted out, data on the bus is simultaneously being shifted in.

SMB0DAT always contains the last data byte present on the bus. In the event of lost arbitration, the transition from

master transmitter to slave receiver is made with the correct data or address in SMB0DAT.

Figure 15.7. SMB0DAT: SMBus Data Register

Bits7-0: SMB0DAT: SMBus Data.

The SMB0DAT register contains a byte of data to be transmitted on the SMBus serial interface or a

byte that has just been received on the SMBus serial interface. The CPU can read from or write to this

ister remains stable as long as the SI flag is set. When the SI flag is not set, the system may be in the

process of shifting data in/out and the CPU should not attempt to access this register.

R/W R/W R/W R/W R/W R/W R/W R/W Reset Value

00000000

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

SFR Address:

0xC2

1 2 ... 133 134 135 136 137 138 139 140 141 142 143 ... 203 204

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Silicon Laboratories Stepper Machine Specifications Page 138